公开(公告)号：US09406403B2

公开(公告)日：2016-08-02

申请号：US13926155

申请日：2013-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Vilas Sridharan ,  James M. O'Connor

IPC: G11C29/00 ,  G11C11/401

CPC classification number: G11C29/76 ,  G11C11/401

Abstract: A memory subsystem employs spare memory cells external to one or more memory devices. In some embodiments, a processing system uses the spare memory cells to replace individual selected cells at the protected memory, whereby the selected cells are replaced on a cell-by-cell basis, rather than exclusively on a row-by-row, column-by-column, or block-by-block basis. This allows faulty memory cells to be replaced efficiently, thereby improving memory reliability and manufacturing yields, without requiring large blocks of spare memory cells.

Abstract translation: 存储器子系统在一个或多个存储器件外部使用备用存储器单元。 在一些实施例中，处理系统使用备用存储器单元来替换受保护存储器处的各个所选择的单元，由此所选择的单元在逐个单元的基础上被替代，而不是仅排列在逐列的列上， 逐列或逐块的基础。 这样可以有效地更换故障存储单元，从而提高存储器的可靠性和制造成本，而不需要大量的备用存储单元。

公开(公告)号：US09286948B2

公开(公告)日：2016-03-15

申请号：US13941791

申请日：2013-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Nuwan S. Jayasena ,  James M. O'Connor ,  Yasuko Eckert

IPC: G11C5/02 ,  G06F12/02 ,  G06F12/10

CPC classification number: G11C5/025 ,  G06F3/0608 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/10 ,  G06F17/30477 ,  G06F17/30982 ,  G06F2212/60 ,  G11C5/02 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: An integrated circuit (IC) package includes a stacked-die memory device. The stacked-die memory device includes a set of one or more stacked memory dies implementing memory cell circuitry. The stacked-die memory device further includes a set of one or more logic dies electrically coupled to the memory cell circuitry. The set of one or more logic dies includes a query controller and a memory controller. The memory controller is coupleable to at least one device external to the stacked-die memory device. The query controller is to perform a query operation on data stored in the memory cell circuitry responsive to a query command received from the external device.

Abstract translation: 集成电路（IC）封装包括堆叠式存储器件。 堆叠式存储器件包括一组实现存储器单元电路的一个或多个堆叠存储器管芯。 堆叠裸片存储器件还包括电耦合到存储单元电路的一组或多个逻辑管芯。 一个或多个逻辑管芯的集合包括查询控制器和存储器控制器。 存储器控制器可耦合到堆叠式存储器件外部的至少一个器件。 查询控制器响应于从外部设备接收的查询命令，对存储在存储单元电路中的数据执行查询操作。

公开(公告)号：US20150293845A1

公开(公告)日：2015-10-15

申请号：US14250474

申请日：2014-04-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lisa R. Hsu ,  James M. O'Connor ,  Vilas K. Sridharan ,  Gabriel H. Loh ,  Nuwan S. Jayasena ,  Bradford M. Beckmann

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0811 ,  G06F12/1009 ,  G06F2212/283 ,  G06F2212/651

Abstract: Described is a system and method for a multi-level memory hierarchy. Each level is based on different attributes including, for example, power, capacity, bandwidth, reliability, and volatility. In some embodiments, the different levels of the memory hierarchy may use an on-chip stacked dynamic random access memory, (providing fast, high-bandwidth, low-energy access to data) and an off-chip non-volatile random access memory, (providing low-power, high-capacity storage), in order to provide higher-capacity, lower power, and higher-bandwidth performance. The multi-level memory may present a unified interface to a processor so that specific memory hardware and software implementation details are hidden. The multi-level memory enables the illusion of a single-level memory that satisfies multiple conflicting constraints. A comparator receives a memory address from the processor, processes the address and reads from or writes to the appropriate memory level. In some embodiments, the memory architecture is visible to the software stack to optimize memory utilization.

Abstract translation: 描述了用于多级存储器层次结构的系统和方法。 每个级别都是基于不同的属性，包括功率，容量，带宽，可靠性和波动性。 在一些实施例中，存储器层级的不同级别可以使用片上堆叠的动态随机存取存储器（提供对数据的快速，高带宽，低能量访问）和片外非易失性随机存取存储器， （提供低功耗，大容量存储），以提供更高容量，更低功耗和更高带宽的性能。 多级存储器可以向处理器呈现统一的接口，从而隐藏特定的存储器硬件和软件实现细节。 多级存储器能够实现满足多个冲突约束的单级存储器的错觉。 比较器从处理器接收存储器地址，处理地址并读取或写入适当的存储器级别。 在一些实施例中，存储器架构对于软件堆栈是可见的以优化存储器利用。

公开(公告)号：US20150199126A1

公开(公告)日：2015-07-16

申请号：US14152003

申请日：2014-01-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Gabriel H. Loh ,  James M. O'Connor ,  Niladrish Chatterjee

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0647 ,  G06F3/0685 ,  G06F12/0292 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/0897 ,  G06F2212/205 ,  G11C11/005 ,  Y02D10/13

Abstract: A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture type and a second set of one or more memory dies implementing second memory cell circuitry of a second memory architecture type different than the first memory architecture type. The die-stacked hybrid memory device further includes a set of one or more logic dies electrically coupled to the first and second sets of one or more memory dies, the set of one or more logic dies comprising a memory interface and a page migration manager, the memory interface coupleable to a device external to the die-stacked hybrid memory device, and the page migration manager to transfer memory pages between the first set of one or more memory dies and the second set of one or more memory dies.

Abstract translation: 芯片堆叠的混合存储器设备实现实现第一存储器架构类型的第一存储器单元电路的一个或多个存储器管芯的第一组和执行第二存储器架构类型不同的第二存储器单元电路的一个或多个存储器管芯的第二组 比第一个内存架构类型。 芯片堆叠式混合存储器件还包括电耦合到一个或多个存储器管芯的第一和第二组的一个或多个逻辑管芯组，该组一个或多个逻辑管芯包括存储器接口和页迁移管理器， 所述存储器接口可耦合到所述管芯堆叠式混合存储器件外部的器件，以及所述页面迁移管理器，用于在所述第一组一个或多个存储器管芯与所述第二组一个或多个存储器管芯之间传送存储器页。

公开(公告)号：US09075730B2

公开(公告)日：2015-07-07

申请号：US13725011

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Mithuna S. Thottethodi ,  Gabriel H. Loh ,  James M. O'Connor ,  Yasuko Eckert ,  Bradford M. Beckmann

IPC: G06F12/08

CPC classification number: G06F12/0871 ,  G06F12/0848

Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache and one or more sources for memory requests. In response to receiving a request to allocate data of a first type, a cache controller allocates the data in the cache responsive to determining a limit of an amount of data of the first type permitted in the cache is not reached. The controller maintains an amount and location information of the data of the first type stored in the cache. Additionally, the cache may be partitioned with each partition designated for storing data of a given type. Allocation of data of the first type is dependent at least upon the availability of a first partition and a limit of an amount of data of the first type in a second partition.

Abstract translation: 一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。 计算系统包括缓存和用于存储器请求的一个或多个源。 响应于接收到分配第一类型的数据的请求，高速缓存控制器响应于确定未达到高速缓存中允许的第一类型的数据量的极限而分配缓存中的数据。 控制器维护存储在高速缓存中的第一类型的数据的量和位置信息。 此外，可以用指定用于存储给定类型的数据的每个分区对高速缓存进行分区。 第一类型的数据的分配至少依赖于第一分区的可用性和第二分区中第一类型的数据量的限制。

公开(公告)号：US09021207B2

公开(公告)日：2015-04-28

申请号：US13723093

申请日：2012-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Edward J. McLellan ,  Paul Keltcher ,  Srilatha Manne ,  Richard E. Klass ,  James M. O'Connor

IPC: G06F12/12

CPC classification number: G06F12/121 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/502 ,  G06F2212/601 ,  Y02D10/13

Abstract: In response to a processor core exiting a low-power state, a cache is set to a minimum size so that fewer than all of the cache's entries are available to store data, thus reducing the cache's power consumption. Over time, the size of the cache can be increased to account for heightened processor activity, thus ensuring that processing efficiency is not significantly impacted by a reduced cache size. In some embodiments, the cache size is increased based on a measured processor performance metric, such as an eviction rate of the cache. In some embodiments, the cache size is increased at regular intervals until a maximum size is reached.

Abstract translation: 响应处理器核心退出低功率状态，将高速缓存设置为最小大小，使得少于所有高速缓存的条目可用于存储数据，从而减少高速缓存的功耗。 随着时间的推移，可以增加高速缓存的大小以考虑到处理器活动的增加，从而确保处理效率不受减小的高速缓存大小的显着影响。 在一些实施例中，基于所测量的处理器性能度量（例如高速缓存的逐出速率）来增加高速缓存大小。 在一些实施例中，高速缓存大小以规则的间隔增加，直到达到最大大小。

公开(公告)号：US20150019834A1

公开(公告)日：2015-01-15

申请号：US13939380

申请日：2013-07-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  James M. O'Connor

IPC: G06F3/06

CPC classification number: G06F12/0868 ,  G06F12/023 ,  G06F2212/401

Abstract: A system includes a device coupleable to a first memory. The device includes a second memory to cache data from the first memory. The second memory is to store a set of compressed pages of the first memory and a set of page descriptors. Each compressed page includes a set of compressed data blocks. Each page descriptor represents a corresponding page and includes a set of location identifiers that identify the locations of the compressed data blocks of the corresponding page in the second memory. The device further includes compression logic to compress data blocks of a page to be stored to the second memory and decompression logic to decompress compressed data blocks of a page accessed from the second memory.

Abstract translation: 系统包括可耦合到第一存储器的设备。 该设备包括用于缓存来自第一存储器的数据的第二存储器。 第二存储器是存储第一存储器的一组压缩页面和一组页面描述符。 每个压缩页面包括一组压缩数据块。 每个页面描述符表示对应的页面，并且包括一组位置标识符，其标识第二存储器中对应页面的压缩数据块的位置。 该设备还包括压缩逻辑以将要存储的页面的数据块压缩到第二存储器和解压缩逻辑以解压缩从第二存储器访问的页面的压缩数据块。

公开(公告)号：US20150016172A1

公开(公告)日：2015-01-15

申请号：US13941791

申请日：2013-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Nuwan S. Jayasena ,  James M. O'Connor ,  Yasuko Eckert

IPC: G11C5/02

CPC classification number: G11C5/025 ,  G06F3/0608 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/10 ,  G06F17/30477 ,  G06F17/30982 ,  G06F2212/60 ,  G11C5/02 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: An integrated circuit (IC) package includes a stacked-die memory device. The stacked-die memory device includes a set of one or more stacked memory dies implementing memory cell circuitry. The stacked-die memory device further includes a set of one or more logic dies electrically coupled to the memory cell circuitry. The set of one or more logic dies includes a query controller and a memory controller. The memory controller is coupleable to at least one device external to the stacked-die memory device. The query controller is to perform a query operation on data stored in the memory cell circuitry responsive to a query command received from the external device.

Abstract translation: 集成电路（IC）封装包括堆叠式存储器件。 堆叠式存储器件包括一组实现存储器单元电路的一个或多个堆叠存储器管芯。 堆叠裸片存储器件还包括电耦合到存储单元电路的一组或多个逻辑管芯。 一个或多个逻辑管芯的集合包括查询控制器和存储器控制器。 存储器控制器可耦合到堆叠式存储器件外部的至少一个器件。 查询控制器响应于从外部设备接收的查询命令，对存储在存储单元电路中的数据执行查询操作。

公开(公告)号：US20140181458A1

公开(公告)日：2014-06-26

申请号：US13726143

申请日：2012-12-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel H. Loh ,  Bradford M. Beckmann ,  James M. O'Connor ,  Michael Ignatowski ,  Michael J. Schulte ,  Lisa R. Hsu ,  Nuwan S. Jayasena

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A die-stacked memory device incorporates a data translation controller at one or more logic dies of the device to provide data translation services for data to be stored at, or retrieved from, the die-stacked memory device. The data translation operations implemented by the data translation controller can include compression/decompression operations, encryption/decryption operations, format translations, wear-leveling translations, data ordering operations, and the like. Due to the tight integration of the logic dies and the memory dies, the data translation controller can perform data translation operations with higher bandwidth and lower latency and power consumption compared to operations performed by devices external to the die-stacked memory device.

Abstract translation: 芯片堆叠存储器件在器件的一个或多个逻辑管芯上并入数据转换控制器，以提供数据转换服务，用于存储在芯片堆叠存储器件中或从芯片堆叠的存储器件中取出的数据。 由数据转换控制器实现的数据转换操作可以包括压缩/解压缩操作，加密/解密操作，格式转换，磨损均衡转换，数据排序操作等。 由于逻辑管芯和存储器管芯的紧密集成，与堆叠式存储器件外部的器件执行的操作相比，数据转换控制器可以执行具有更高带宽和更低延迟和功耗的数据转换操作。

公开(公告)号：US20140156975A1

公开(公告)日：2014-06-05

申请号：US13690841

申请日：2012-11-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Vilas SRIDHARAN ,  James M. O'Connor ,  Steven K. Reinhardt ,  Nuwan S. Jayasena ,  Michael J. Schulte ,  Dean A. Liberty

IPC: G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/3851 ,  G06F9/3887 ,  G06F11/1641 ,  G06F11/1691 ,  G06F11/1695

Abstract: In some embodiments, a method for improving reliability in a processor is provided. The method can include replicating input data for first and second lanes of a processor, the first and second lanes being located in a same cluster of the processor and the first and second lanes each generating a respective value associated with an instruction to be executed in the respective lane, and responsive to a determination that the generated values do not match, providing an indication that the generated values do not match.

Abstract translation: 在一些实施例中，提供了一种用于提高处理器中的可靠性的方法。 该方法可以包括为处理器的第一和第二通道复制输入数据，第一和第二通道位于处理器的相同簇中，并且第一和第二通道各自产生与将要执行的指令相关联的相应值 并且响应于确定所生成的值不匹配，提供所生成的值不匹配的指示。