公开(公告)号：US5363332A

公开(公告)日：1994-11-08

申请号：US860442

申请日：1992-03-30

申请人： Fumio Murabayashi ,  Takashi Hotta ,  Masahiro Iwamura ,  Akiyoshi Osumi

发明人： Fumio Murabayashi ,  Takashi Hotta ,  Masahiro Iwamura ,  Akiyoshi Osumi

IPC分类号： H03K19/013 ,  H03K19/0175 ,  H03K19/018 ,  G11C8/00 ,  H01L27/06

CPC分类号： H03K19/013 ,  H03K19/017518 ,  H03K19/01806

摘要： A semiconductor integrated circuit device is arranged to have a plurality of logic circuit blocks, a data signal path for interconnecting logic circuit blocks and for providing a function of interfacing a current-driven signal. The logic circuit block on a signal output side includes an output circuit connected to the data signal path and a switching element formed of an NMOS transistor for controlling current flowing through the data signal path in response to an input signal applied to an input terminal of the output circuit. The logic circuit block on a signal input side includes an input circuit connected to the data signal path. The input circuit includes a bipolar transistor having an emitter connected to a constant current source, a collector forming an output terminal, and a base set at a fixed potential. The data signal path led from the output circuit is connected to the emitter of the bipolar transistor. The arrangement results in reducing a signal amplitude on the signal bus, thereby speeding up the transmission of the data signal and reducing noise of the signal.

摘要翻译： 半导体集成电路器件被布置为具有多个逻辑电路块，用于互连逻辑电路块的数据信号路径，并且用于提供与电流驱动信号接口的功能。 信号输出侧的逻辑电路块包括连接到数据信号路径的输出电路和由NMOS晶体管形成的开关元件，用于响应于施加到数据信号路径的输入端子的输入信号来控制流过数据信号路径的电流 输出电路。 信号输入侧的逻辑电路块包括连接到数据信号路径的输入电路。 输入电路包括具有连接到恒流源的发射极，形成输出端的集电极和固定电位的基极的双极晶体管。 从输出电路引出的数据信号路径连接到双极晶体管的发射极。 该结构可以减少信号总线上的信号幅度，从而加速数据信号的传输并降低信号的噪声。

公开(公告)号：US5362998A

公开(公告)日：1994-11-08

申请号：US193643

申请日：1994-02-07

申请人： Masahiro Iwamura ,  Hideo Maejima ,  Atsuo Watanabe ,  Kazutaka Mori

发明人： Masahiro Iwamura ,  Hideo Maejima ,  Atsuo Watanabe ,  Kazutaka Mori

IPC分类号： H01L27/06 ,  H01L21/8249 ,  H03K17/56 ,  H03K17/567 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/02

CPC分类号： H03K19/0136 ,  H03K19/09448

摘要： A composite circuit device of bipolar transistors and MOS transistors has a series connection of an NPN transistor for pull-up and a PNP transistor for pull-down. The composite circuit device has independent base drive circuits so provided that the base of the NPN transistor for pull-up is electrically isolated from the base of the PNP transistor for pull-down during the on-off switching operation. The composite circuit device is also provided with base precharge circuitry for pre-charging the base of the PNP transistor during the off operation state thereof. A composite circuit is also provided with circuitry for enhancing the turn-on switching speed of the pull-down PNP transistor. Additionally, a composite circuit of bipolar transistors and MOS transistors is constituted by a switch having a high input impedance and low on-resistance which can be applied as a component of an electronic circuit.

摘要翻译： 双极晶体管和MOS晶体管的复合电路器件具有用于上拉的NPN晶体管和用于下拉的PNP晶体管的串联连接。 复合电路器件具有独立的基极驱动电路，使得用于上拉的NPN晶体管的基极与PNP晶体管的基极电隔离，用于在截止开关操作期间进行下拉。 复合电路器件还设置有用于在其关断操作状态期间对PNP晶体管的基极进行预充电的基极预充电电路。 复合电路还提供有用于增强下拉PNP晶体管的导通开关速度的电路。 此外，双极晶体管和MOS晶体管的复合电路由具有高输入阻抗和低导通电阻的开关构成，其可以用作电子电路的组件。

公开(公告)号：US5285414A

公开(公告)日：1994-02-08

申请号：US765838

申请日：1991-09-26

申请人： Tatsumi Yamauchi ,  Masahiro Iwamura ,  Kazutaka Mori

发明人： Tatsumi Yamauchi ,  Masahiro Iwamura ,  Kazutaka Mori

IPC分类号： G11C7/12 ,  G11C11/419 ,  G11C11/40

CPC分类号： G11C7/12 ,  G11C11/419

摘要： A semiconductor memory comprises a write driver which is provided to correspond to respective data line and by which data lines connected with a memory cell through the control of a word line are driven in a write operation. The write driver includes MOSFETs of first group and MOSFETs of second group. In a case where a write enable signal does not designate the write operation, the MOSFETs of the first group are normally in ON states to pull up the data lines. Besides, in a case where the write enable signal designates the write operation, each of them operates in accordance with the value of input data, to maintain the ON states and pull up the corresponding data line in case of driving the data line to a "high" level and to fall into OFF states in case of driving the data line to a "low" level. On the other hand, the MOSFETs of the second group are normally in OFF states. Besides, in the case where the write enable signal designates the write operation, each of them operates in accordance with the value of the input data, to fall into ON state and draw the corresponding data line to the low level in the case of driving the data lines to the low level.

摘要翻译： 半导体存储器包括写驱动器，其被提供以对应于相应的数据线，并且通过字线的控制与存储器单元连接的数据线在写入操作中被驱动。 写驱动器包括第一组的MOSFET和第二组的MOSFET。 在写入使能信号不表示写入操作的情况下，第一组的MOSFET通常处于ON状态以上拉数据线。 此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作，以在将数据线驱动到“ 高“电平并且在将数据线驱动到”低“电平的情况下落入OFF状态。 另一方面，第二组的MOSFET通常处于OFF状态。 此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作以进入ON状态，并且在驱动该操作的情况下将相应的数据线绘制到低电平 数据线到低电平。

公开(公告)号：US5245224A

公开(公告)日：1993-09-14

申请号：US845136

申请日：1992-03-03

申请人： Yukio Suzuki ,  Ikuro Masuda ,  Masahiro Iwamura ,  Shinji Kadono ,  Akira Uragami ,  Masayoshi Yoshimura ,  Toshiaki Matsubara

发明人： Yukio Suzuki ,  Ikuro Masuda ,  Masahiro Iwamura ,  Shinji Kadono ,  Akira Uragami ,  Masayoshi Yoshimura ,  Toshiaki Matsubara

IPC分类号： H03K19/0175 ,  H03K19/018 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/177

CPC分类号： H03K19/09448 ,  H03K19/017518 ,  H03K19/01806 ,  H03K19/09429

摘要： In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

摘要翻译： 在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。 因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。 类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由 双极晶体管。 因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

公开(公告)号：US5103120A

公开(公告)日：1992-04-07

申请号：US636892

申请日：1991-01-02

申请人： Yukio Suzuki ,  Ikuro Masuda ,  Masahiro Iwamura ,  Shinji Kadono ,  Akira Uragami ,  Masayoshi Yoshimura ,  Toshiaki Matsubara

发明人： Yukio Suzuki ,  Ikuro Masuda ,  Masahiro Iwamura ,  Shinji Kadono ,  Akira Uragami ,  Masayoshi Yoshimura ,  Toshiaki Matsubara

IPC分类号： H03K19/00 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/177

CPC分类号： H03K19/09448 ,  H03K19/017518 ,  H03K19/01806 ,  H03K19/09425 ,  H03K19/09429 ,  H01L2924/0002

摘要： In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

摘要翻译： 在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。 因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。 类似地，在用于CMOS电平操作的内部逻辑块的CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由 双极晶体管。 因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

公开(公告)号：US4860148A

公开(公告)日：1989-08-22

申请号：US37851

申请日：1987-04-13

申请人： Masahiro Iwamura ,  Ikuro Masuda ,  Hideaki Uchida

发明人： Masahiro Iwamura ,  Ikuro Masuda ,  Hideaki Uchida

IPC分类号： H03K17/00 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H03K17/08 ,  H03K19/003 ,  H03K19/01 ,  H03K19/0948

CPC分类号： H03K17/08 ,  H01L27/0248

摘要： A semiconductor integrated circuit device is provided with an input and/or an output terminal and at least one semiconductor device. The circuit has a resistor provided between the input terminal and/or the output terminal and one of the at least one semiconductor devices and an electronic switch connected in parallel with the resistor. The electronic switch is on-off controlled so as to exhibit a relatively low impedance when the semiconductor device is in operation and a relatively high impedance when the semiconductor device is not in operation. Thus, the semiconductor integrated circuit device is operable at a higher speed with an improved reliability and/or with controllable response characteristics, as compared with the conventional device.

摘要翻译： 半导体集成电路器件设置有输入和/或输出端子和至少一个半导体器件。 电路具有设置在输入端子和/或输出端子之间的电阻器，以及至少一个半导体器件中的一个和与电阻器并联连接的电子开关。 当半导体器件处于工作状态时，电子开关被开关控制，以便表现出相对较低的阻抗，当半导体器件不工作时，电子开关具有较高的阻抗。 因此，与常规器件相比，半导体集成电路器件可以以更高的速度操作，具有改善的可靠性和/或具有可控的响应特性。

公开(公告)号：US4801983A

公开(公告)日：1989-01-31

申请号：US899399

申请日：1986-08-22

申请人： Masahiro Ueno ,  Masahiro Iwamura ,  Kozaburo Kurita ,  Ikuro Masuda

发明人： Masahiro Ueno ,  Masahiro Iwamura ,  Kozaburo Kurita ,  Ikuro Masuda

IPC分类号： H03K19/0944 ,  H01L21/82 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H03K17/687 ,  H03K17/693 ,  H03K19/094 ,  H03K19/0952 ,  H01L27/04 ,  G11C11/40

CPC分类号： H03K17/687 ,  H01L27/0727

摘要： A unidirectional switching circuit having no charge storage effect for performing a high-speed switching operation is disclosed in which one of the anode and cathode terminals of a Schottky-barrier diode is connected to one of the source and drain terminals of a field effect transistor to form the series combination of the Schottky-barrier diode and the field effect transistor, that one of end terminals of the series combination which exists on the anode side of the diode, is used as an input terminal, the other end terminal existing on the cathode side is used as an output terminal, the gate electrode of the field effect transistor is used as a switching control electrode, and a current flowing through the switching circuit in a direction from the input terminal to the output terminal is controlled in accordance with a signal applied to the switching control electrode.

摘要翻译： 公开了一种不进行高速开关动作的电荷存储效应的单向开关电路，其中肖特基势垒二极管的阳极和阴极端子之一连接到场效应晶体管的源极和漏极端子之一， 形成肖特基势垒二极管和场效应晶体管的串联组合，存在于二极管的阳极侧的串联组合的端子之一用作输入端子，另一端子存在于阴极 侧用作输出端子，场效应晶体管的栅电极用作开关控制电极，并且根据信号控制沿着从输入端到输出端的方向流过开关电路的电流 施加到开关控制电极。

公开(公告)号：US4789958A

公开(公告)日：1988-12-06

申请号：US703171

申请日：1985-02-19

申请人： Hideo Maejima ,  Takashi Hotta ,  Ikuro Masuda ,  Masahiro Iwamura ,  Kouzaburou Kurita ,  Masahiro Ueno

发明人： Hideo Maejima ,  Takashi Hotta ,  Ikuro Masuda ,  Masahiro Iwamura ,  Kouzaburou Kurita ,  Masahiro Ueno

IPC分类号： G06F5/01 ,  G06F7/50 ,  G06F7/508 ,  G06F13/40 ,  G06F15/78

CPC分类号： G06F7/508 ,  G06F13/4077 ,  G06F15/7832 ,  G06F5/015 ,  G06F2207/3872 ,  Y02B60/1207 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

摘要： A carry-look-ahead adder is provided which is implemented as a semiconductor integrated circuit. The integrated circuit includes a bipolar transistor coupled to the output terminal for providing an output indicative of the arithmetic operation. Impedance elements are coupled to the bipolar transistor and at least one FET is provided to control the on/off state of the bipolar transistor.

摘要翻译： 提供了作为半导体集成电路实现的进位前视加法器。 集成电路包括耦合到输出端的双极晶体管，用于提供表示算术运算的输出。 阻抗元件耦合到双极晶体管，并且提供至少一个FET以控制双极晶体管的导通/截止状态。

公开(公告)号：US4228430A

公开(公告)日：1980-10-14

申请号：US860117

申请日：1977-12-13

申请人： Masahiro Iwamura ,  Nagaharu Hamada ,  Schigeo Kuboki ,  Kenichi Fukushima

发明人： Masahiro Iwamura ,  Nagaharu Hamada ,  Schigeo Kuboki ,  Kenichi Fukushima

IPC分类号： G09G3/20 ,  G09G3/00 ,  G09G5/08 ,  G09G5/10 ,  G09G5/30 ,  G06F3/14

CPC分类号： G09G5/30 ,  G09G5/08

摘要： Disclosed is a raster scanning type CRT display apparatus having a microprogrammed processor for primarily controlling the input and output of data to and from an external information source. This CRT display apparatus comprises a plurality of cursor controlling registers having their contents set by the processor. The contents of these registers define the configuration of a cursor for displaying a data entry position on its screen, the decision with respect to the blinking of the cursor, and a period of the blinking.

摘要翻译： 公开了一种光栅扫描型CRT显示装置，其具有微程序处理器，用于主要控制与外部信息源的数据的输入和输出。 该CRT显示装置包括多个光标控制寄存器，其具有由处理器设置的内容。 这些寄存器的内容定义了用于在其屏幕上显示数据输入位置的光标的配置，关于光标的闪烁的决定以及闪烁的周期。

公开(公告)号：US4129859A

公开(公告)日：1978-12-12

申请号：US766728

申请日：1977-02-08

申请人： Masahiro Iwamura ,  Nagaharu Hamada ,  Toshitaka Hara ,  Nobuo Sato

发明人： Masahiro Iwamura ,  Nagaharu Hamada ,  Toshitaka Hara ,  Nobuo Sato

IPC分类号： G09G5/32 ,  G09G5/34 ,  G06F3/14

CPC分类号： G09G5/343

摘要： A raster scan type CRT display system is disclosed which has a randomly accessable refresh memory. The display system comprises column and row start address registers for defining a read start address for the refresh memory, column and row address counters for counting the contents of the column and row start address registers as start positions to generate a read address of the refresh memory for display, column and row cursor registors for defining a data entry position on a CRT screen, and column and row address generators for generating an entry address for the refresh memory based on the contents of the column and row start address registers and the contents of the column and row cursor registers, whereby a rolling or shifting of the image is effected and the refresh memory can be accessed by a processor for read/write operation without the need to monitor the image rolling.

摘要翻译： 公开了一种具有随机存取的刷新存储器的光栅扫描型CRT显示系统。 显示系统包括用于定义刷新存储器的读起始地址的列和行起始地址寄存器，用于对列的内容进行计数的列和行地址计数器以及行起始地址寄存器作为起始位置，以生成刷新存储器的读地址 用于在CRT屏幕上定义数据输入位置的显示器，列和行光标注册器，以及用于根据列和行起始地址寄存器的内容产生刷新存储器的入口地址的列和行地址生成器， 列和行光标寄存器，从而影响图像的滚动或移位，并且可以由处理器访问刷新存储器以进行读/写操作，而不需要监视图像滚动。