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    Method and apparatus for detecting an initialization signal and a command packet error in packetized dynamic random access memories
    51.
    发明授权
    Method and apparatus for detecting an initialization signal and a command packet error in packetized dynamic random access memories 有权
    用于检测分组化动态随机存取存储器中的初始化信号和命令包错误的方法和装置

    公开(公告)号：US6167495A

    公开(公告)日：2000-12-26

    申请号：US141467

    申请日：1998-08-27

    申请人： Brent Keeth ,  Troy A. Manning

    发明人： Brent Keeth ,  Troy A. Manning

    IPC分类号： G11C7/10 ,  G11C7/20 ,  G06F12/16

    CPC分类号： G11C7/1072 ,  G11C7/20

    摘要： A system for detecting an initialization flag signal and distinguishing it from a normal flag signal having half the duration of the initialization flag signal. The initialization flag detection system may be included in the command buffer of a packetized DRAM that is used in a computer system. In one embodiment, the initialization flag detection system includes a pair of shift registers receiving the flag signal at their respective data inputs. One of the shift registers is clocked by a signal corresponding to an externally applied to command clock signal, while the other shift register is clocked by a quadrature clock signal. Together, the shift registers store a number of samples taken over a duration that is longer than the duration of the normal flag signal. The outputs of the shift registers are applied to a logic circuit, such as a NAND gate, that generates an initialization signal when all of the samples stored in the shift registers correspond to the logic levels of the flag signal. In another embodiment, the initialization flag detection system includes a plurality of latches receiving the flag signals at their data inputs. The latches are clocked by respective strobe signals corresponding to the command clock signal, but having phases that differ from each other. The outputs of the latches are applied to a logic circuit, such as a NAND) gate. Finally, in another embodiment of the invention, the bits of the command packet are sampled along with the flag signal and compared to the samples of the flag signal to detect when a command packet having a predetermined pattern does not correspond to a flag signal having a predetermined pattern.

    摘要翻译： 用于检测初始化标志信号并将其与具有初始化标志信号的持续时间的一半的正常标志信号区分开的系统。 初始化标志检测系统可以包括在计算机系统中使用的分组化DRAM的命令缓冲器中。 在一个实施例中，初始化标志检测系统包括在它们各自的数据输入端接收标志信号的一对移位寄存器。 一个移位寄存器由对应于外部施加到命令时钟信号的信号计时，而另一个移位寄存器由正交时钟信号计时。 移位寄存器一起存储长于正常标志信号的持续时间的持续时间的采样数量。 当存储在移位寄存器中的所有采样都对应于标志信号的逻辑电平时，移位寄存器的输出被施加到逻辑电路，例如与非门，其产生初始化信号。 在另一个实施例中，初始化标志检测系统包括在其数据输入端接收标志信号的多个锁存器。 锁存器由对应于命令时钟信号的相应选通信号计时，但具有彼此不同的相位。 锁存器的输出被施加到逻辑电路，例如NAND门）。 最后，在本发明的另一个实施例中，命令分组的比特与标志信号一起被采样，并与标志信号的样本进行比较，以检测何时具有预定模式的命令分组不对应于具有 预定模式。

    Multi-bank memory input/output line selection
    52.
    发明授权
    Multi-bank memory input/output line selection 有权
    多组存储器输入/输出线选择

    公开(公告)号：US6122217A

    公开(公告)日：2000-09-19

    申请号：US244573

    申请日：1999-02-04

    申请人： Brent Keeth ,  Troy A. Manning

    发明人： Brent Keeth ,  Troy A. Manning

    IPC分类号： G11C7/10 ,  G11C8/12 ,  G11C8/00

    CPC分类号： G11C8/12 ,  G11C7/1006

    摘要： A multi-bank memory includes memory cells arranged in individually selectable banks that share column select signals. The memory cells are addressed by a row decoder that activates word lines to couple data onto digit lines. The digit lines are coupled to input/output lines through first and second series-connected switches. The first switches are input/output switches that are controlled by column select signals that are shared between multiple banks. The second switches are bank select switches that are controlled by a bank decoder, for coupling only one of the banks to input/output lines and isolating the other banks from input/output lines. The invention reduces timing requirements between operations in different banks, and allows concurrent operations in different banks, thereby increasing the speed at which the memory operates.

    摘要翻译： 多存储体存储器包括布置在单独可选择的存储体中的存储单元，其共享列选择信号。 存储器单元由行解码器寻址，其激活字线以将数据耦合到数字线上。 数字线通过第一和第二串联连接的开关耦合到输入/输出线。 第一个开关是由多个银行之间共享的列选择信号控制的输入/输出开关。 第二开关是由银行解码器控制的存储体选择开关，用于仅将一个存储体耦合到输入/输出线路，并将其它存储体与输入/输出线路隔离。 本发明减少了不同库中的操作之间的时序要求，并且允许在不同的存储体中进行并行操作，从而增加存储器操作的速度。

    Method and system for generating reference voltages for signal receivers
    53.
    发明授权
    Method and system for generating reference voltages for signal receivers 有权
    用于产生信号接收机参考电压的方法和系统

    公开(公告)号：US07577212B2

    公开(公告)日：2009-08-18

    申请号：US10930543

    申请日：2004-08-30

    申请人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

    发明人： Brent Keeth ,  Joo S. Choi ,  George E. Pax ,  Ronnie M. Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy A. Manning ,  Roy E. Greeff ,  Greg King ,  Brian Johnson

    IPC分类号： H03K9/00

    CPC分类号： H04L25/062

    摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

    摘要翻译： 用于产生用于存储器件信号接收器的参考电压的方法和系统以校准模式或正常操作模式工作。 在校准模式下，参考电压的幅度逐渐变化，并且数字信号图案在每个参考电压下耦合到接收器。 分析接收机的输出以确定接收机是否可以在每个参考电压电平下准确地传递信号模式。 记录允许接收器精确地通过信号图案的参考电压范围，并且在该范围的大致中点处计算最终参考电压。 在正常操作期间将该最终参考电压施加到接收器。