公开(公告)号：US20050170561A1

公开(公告)日：2005-08-04

申请号：US10844877

申请日：2004-05-12

申请人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/055 ,  H01L23/10 ,  H01L31/0203

CPC分类号： H01L23/055 ,  H01L21/50 ,  H01L23/10 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/05599 ,  H01L2924/00

摘要： A fabrication method of a semiconductor package with a photosensitive chip is provided. A substrate having a core is prepared. An interposer is mounted on the substrate, with a peripheral portion of the substrate exposed from the interposer. A molding process is performed and the substrate is clamped between an upper mold and a lower mold, with the interposer received in an upwardly-recessed cavity of the upper mold. A molding compound is injected into the upwardly-recessed cavity to form a dam on the peripheral portion of the substrate. Then the upper and lower molds and the interposer are removed from the substrate to expose area covered by the interposer on the substrate. At least one photosensitive chip is mounted on the exposed area of the substrate. A lid seals the dam such that the chip is received in a space defined by the substrate, the dam and the lid.

摘要翻译： 提供了具有感光芯片的半导体封装的制造方法。 制备具有芯的衬底。 插入器安装在衬底上，衬底的周边部分从插入件露出。 进行成型工艺，并且将基板夹在上模具和下模具之间，其中插入件容纳在上模具的向上凹入的空腔中。 将模塑料注入到上凹腔中以在基材的周边部分上形成坝。 然后将上模和下模和插入件从基板上移除以露出基板上由插入件覆盖的区域。 至少一个感光芯片安装在基板的暴露区域上。 盖子密封大坝，使得芯片被容纳在由基板，坝和盖子限定的空间中。

公开(公告)号：US06667546B2

公开(公告)日：2003-12-23

申请号：US10039884

申请日：2002-01-03

申请人： Chien-Ping Huang ,  Eric Ko ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Eric Ko ,  Chih-Ming Huang

IPC分类号： H01L2310

CPC分类号： H01L24/85 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L2224/05554 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8485 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012

摘要： A ball grid array semiconductor package is proposed, wherein at least a chip is mounted on a substrate, and signal pads on the chip are electrically connected to signal fingers on the substrate by bonding wires. A power plate and a ground plate are each attached at two ends thereof respectively to predetermined positions on the chip and substrate, without interfering with the bonding wires. No power ring or ground ring is necessarily formed on the substrate, thereby reducing restriction on trace routability of the substrate. Further, with no provision of power wires or ground wires, short circuit of the bonding wires is less likely to occur, and thus production yield is enhanced. In addition, the power plate and ground plate provide shielding effect for protecting the chip against external electric-magnetic interference, and are partly in direct contact with the atmosphere for improving heat dissipating efficiency of the semiconductor package.

摘要翻译： 提出了一种球栅阵列半导体封装，其中至少芯片安装在基板上，并且芯片上的信号焊盘通过接合线与基板上的信号指状电连接。 功率板和接地板分别在其两端分别连接到芯片和基板上的预定位置，而不会妨碍接合线。 在基板上不必形成功率环或接地环，从而减少对基板的微量可路由性的限制。 此外，由于不设置电源线或接地线，因此不太可能发生接合线的短路，从而提高了生产率。 此外，功率板和接地板提供屏蔽效果，用于保护芯片免受外部电磁干扰，并且部分地与大气直接接触，以提高半导体封装的散热效率。

公开(公告)号：US08546183B2

公开(公告)日：2013-10-01

申请号：US12241847

申请日：2008-09-30

申请人： Chien-Ping Huang ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Chih-Ming Huang

IPC分类号： H01L21/02

CPC分类号： H01L23/3677 ,  H01L21/4871 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3733 ,  H01L23/4334 ,  H01L23/49548 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/351 ,  Y10T29/49126 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A heat dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted on a chip carrier. A heat sink is mounted on the chip, and includes an insulating core layer, a thin metallic layer formed on each of an upper surface and a lower surface of the insulating core layer and a thermal via hole formed in the insulating core layer. A molding process is performed to encapsulate the chip and the heat sink with an encapsulant to form a package unit. A singulation process is performed to peripherally cut the package unit. A part of the encapsulant above the thin metallic layer on the upper surface of the heat sink is removed, such that the thin metallic layer on the upper surface of the heat sink is exposed, and heat generated by the chip can be dissipated through the heat sink.

摘要翻译： 提供散热半导体封装及其制造方法。 半导体芯片安装在芯片载体上。 散热器安装在芯片上，并且包括绝缘芯层，形成在绝缘芯层的上表面和下表面中的每一个上的薄金属层和形成在绝缘芯层中的热通孔。 进行成型工艺以用密封剂封装芯片和散热器以形成封装单元。 执行单个处理以周边地切割包装单元。 在散热器的上表面上的薄金属层上方的一部分密封剂被去除，使得散热器上表面上的薄金属层被暴露，并且由芯片产生的热量可以通过热量散发 水槽。

公开(公告)号：US08013443B2

公开(公告)日：2011-09-06

申请号：US12727307

申请日：2010-03-19

申请人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Chih-Ming Huang ,  Chien-Ping Huang

发明人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Chih-Ming Huang ,  Chien-Ping Huang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3121 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/3025 ,  H05K3/284 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/0989 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

摘要： An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings for exposing the bond pads. A groove is formed between the paired bond pads and has a length larger than a width of an electronic component mounted on the paired bond pads. The groove is adjacent to one of the paired bond pads and communicates with a corresponding one of the openings where this bond pad is exposed. Accordingly, a clearance between the electronic component and the electronic carrier board can be effectively filled with an insulating resin for encapsulating the electronic component, thereby preventing voids and undesirable electrical bridging between the paired bond pads from occurrence.

摘要翻译： 提供电子载体板及其封装结构。 电子载板包括载体，形成在载体上的至少一对接合焊盘和覆盖载体的保护层。 保护层形成有用于暴露接合焊盘的开口。 在成对的接合焊盘之间形成有一个沟槽，其长度大于安装在成对接合焊盘上的电子部件的宽度。 该沟槽与一对接合焊盘相邻，并与该接合焊盘露出的相应的一个开口连通。 因此，电子部件和电子载体板之间的间隙可以有效地填充用于封装电子部件的绝缘树脂，从而防止成对焊盘之间的空隙和不期望的电桥发生。

公开(公告)号：US07816187B2

公开(公告)日：2010-10-19

申请号：US12204066

申请日：2008-09-04

申请人： Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Yu-Po Wang ,  Chih-Ming Huang

IPC分类号： H01L21/00

CPC分类号： H01L21/4832 ,  H01L21/4857 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

摘要翻译： 提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。 第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。 芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。 该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

公开(公告)号：US07271024B2

公开(公告)日：2007-09-18

申请号：US11163310

申请日：2005-10-13

申请人： Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Yi Chang

发明人： Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Yi Chang

IPC分类号： H01L21/00 ,  H01L31/113

CPC分类号： H01L27/14683 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14634 ,  H01L2224/81801 ,  H01L2224/82 ,  H01L2224/85 ,  H01L2224/86 ,  H01L2924/14 ,  H01L2924/00

摘要： A sensor semiconductor device and a method for fabricating the same are proposed. A plurality of metal bumps and a sensor chip are mounted on a substrate. A dielectric layer and a circuit layer are formed on the substrate, wherein the circuit layer is electrically connected to the metal bumps and the sensor chip. Thus, the sensor chip is electrically connected to the substrate via the circuit layer and the metal bumps. The dielectric layer is formed with an opening for exposing a sensor region of the sensor chip. A light-penetrable lid covers the opening of the dielectric layer, such that light is able to penetrate the light-penetrable lid to reach the sensor region and activate the sensor chip. A plurality of solder balls are mounted on a surface of the substrate free of mounting the sensor chip, for electrically connecting the sensor chip to an external device.

摘要翻译： 提出了一种传感器半导体器件及其制造方法。 多个金属凸块和传感器芯片安装在基板上。 在基板上形成电介质层和电路层，其中电路层电连接到金属凸块和传感器芯片。 因此，传感器芯片经由电路层和金属凸块电连接到基板。 电介质层形成有用于暴露传感器芯片的传感器区域的开口。 透光盖子覆盖电介质层的开口，使得光线能够穿透透光盖子到达传感器区域并激活传感器芯片。 多个焊球安装在基板的表面上，无需安装传感器芯片，用于将传感器芯片电连接到外部设备。

公开(公告)号：US20070034998A1

公开(公告)日：2007-02-15

申请号：US11580560

申请日：2006-10-12

申请人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

IPC分类号： H01L23/02

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00

摘要： A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material filled within the space formed between the semiconductor chip and the glass frame, a build-up layer formed on the glass frame and the semiconductor chip such that the build-up layer is electrically connected to the semiconductor chip, and a plurality of conductive elements mounted on the build-up layer so that the semiconductor chip is electrically connected to external devices. With the use of the glass frame and low-modulus buffer material, the wafer level semiconductor package thus-obtained is free from warpage, chip-crack, and delamination problems and the reliability thereof is enhanced. A method for fabricating the wafer level semiconductor package is also provided.

摘要翻译： 提供具有积层的晶片级半导体封装，其包括具有用于接收其中的半导体芯片的通孔的玻璃框架，填充在形成在半导体芯片和玻璃框架之间的空间内的低模量缓冲材料， 形成在所述玻璃框架和所述半导体芯片上的堆积层，使得所述积层层电连接到所述半导体芯片，以及安装在所述积层层上的多个导电元件，使得所述半导体芯片电连接 到外部设备。 通过使用玻璃框架和低模量缓冲材料，由此获得的晶片级半导体封装没有翘曲，芯片裂纹和分层问题，并且其可靠性得到提高。 还提供了一种用于制造晶片级半导体封装的方法。

公开(公告)号：US20060292741A1

公开(公告)日：2006-12-28

申请号：US11471516

申请日：2006-06-21

申请人： Wen-Tsung Tseng ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

发明人： Wen-Tsung Tseng ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/00

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L23/4334 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A heat-dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted and electrically connected to a substrate. A heat-dissipating structure includes a heat sink and at least one supporting portion, wherein the supporting portion is attached to the substrate at a position outside a predetermined package area for the semiconductor package, and the semiconductor chip is disposed under the heat sink. An encapsulant is formed on the substrate to encapsulate the semiconductor chip and the heat-dissipating structure, wherein a projection area of the encapsulant on the substrate is larger in size than the predetermined package area. A cutting process is performed along edges of the predetermined package area to remove parts of the encapsulant, the supporting portion and the substrate, which are located outside the predetermined package area, so as to form the semiconductor package integrated with the heat-dissipating structure.

摘要翻译： 提供散热半导体封装及其制造方法。 半导体芯片安装并电连接到基板。 散热结构包括散热器和至少一个支撑部分，其中支撑部分在用于半导体封装的预定封装区域外的位置处附接到基板，并且半导体芯片设置在散热器下方。 在基板上形成密封剂以封装半导体芯片和散热结构，其中密封剂在基板上的投影面积大于预定封装面积。 沿着预定包装区域的边缘进行切割处理以去除位于预定包装区域外部的密封剂，支撑部分和基底的部分，以形成与散热结构集成的半导体封装。

公开(公告)号：US06989296B2

公开(公告)日：2006-01-24

申请号：US10844877

申请日：2004-05-12

申请人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

发明人： Chien-Ping Huang ,  Cheng-Hsu Hsiao ,  Chih-Ming Huang

IPC分类号： H01L21/44

CPC分类号： H01L23/055 ,  H01L21/50 ,  H01L23/10 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/05599 ,  H01L2924/00

摘要： A fabrication method of a semiconductor package with a photosensitive chip is provided. A substrate having a core is prepared. An interposer is mounted on the substrate, with a peripheral portion of the substrate exposed from the interposer. A molding process is performed and the substrate is clamped between an upper mold and a lower mold, with the interposer received in an upwardly-recessed cavity of the upper mold. A molding compound is injected into the upwardly-recessed cavity to form a dam on the peripheral portion of the substrate. Then the upper and lower molds and the interposer are removed from the substrate to expose area covered by the interposer on the substrate. At least one photosensitive chip is mounted on the exposed area of the substrate. A lid seals the dam such that the chip is received in a space defined by the substrate, the dam and the lid.

摘要翻译： 提供了具有感光芯片的半导体封装的制造方法。 制备具有芯的衬底。 插入器安装在衬底上，衬底的周边部分从插入件露出。 进行成型工艺，并且将基板夹在上模具和下模具之间，其中插入件容纳在上模具的向上凹入的空腔中。 将模塑料注入到上凹腔中以在基材的周边部分上形成坝。 然后将上模和下模和插入件从基板上移除以露出基板上由插入件覆盖的区域。 至少一个感光芯片安装在基板的暴露区域上。 盖子密封大坝，使得芯片被容纳在由基板，坝和盖子限定的空间中。

公开(公告)号：US06828665B2

公开(公告)日：2004-12-07

申请号：US10319262

申请日：2002-12-13

申请人： Han-Ping Pu ,  Chih-Ming Huang ,  Chien-Ping Huang

发明人： Han-Ping Pu ,  Chih-Ming Huang ,  Chien-Ping Huang

IPC分类号： H01L2302

CPC分类号： H01L23/5385 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/141 ,  H05K1/144 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2224/0401

摘要： A module device of stacked semiconductor packages and a method for fabricating the module device are proposed, wherein a first semiconductor package provided, and at least a second semiconductor package is stacked on and electrically connected to the first semiconductor package. The first semiconductor package includes a chip carrier for mounting at least a chip thereon; a circuit board positioned above and electrically connected to the chip carrier by a plurality of conductive elements; and an encapsulant for encapsulating the chip, conductive elements and encapsulant with a top surface of the circuit board being exposed, allowing the second semiconductor package to be electrically connected to the exposed top surface of the circuit board. As the circuit board is incorporated in the first semiconductor package by means of the encapsulant, it provides preferably reliability and workability for electrically connecting the second semiconductor package to the first semiconductor package.