公开(公告)号：US20060023503A1

公开(公告)日：2006-02-02

申请号：US11056901

申请日：2005-02-11

申请人： Peter Lee

发明人： Peter Lee

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C14/0063 ,  G11C14/00 ,  G11C16/10

摘要： A nonvolatile SRAM array has an array of integrated nonvolatile SRAM circuits arranged in rows and columns on a substrate. Each of the integrated nonvolatile SRAM circuits includes an SRAM cell, a first and second nonvolatile memory element. The SRAM cell has a latched memory element in communication first and second nonvolatile memory elements to receive and permanently retain the digital signal from the latched memory element. A power detection circuit detects a power interruption and a power initiation and communicates the detection of the power interruption and power initiation to the plurality of integrated nonvolatile SRAM circuits. The SRAM cell, upon detection of the power interruption, transmits the digital signal to the first and second nonvolatile memory elements. The SRAM cell of each of the nonvolatile static random access memories upon detection of the power initiation, receives the digital signal from the first and second nonvolatile memory elements.

摘要翻译： 非易失性SRAM阵列具有在基板上以行和列布置的集成非易失性SRAM电路阵列。 每个集成的非易失性SRAM电路包括SRAM单元，第一和第二非易失性存储元件。 SRAM单元在通信第一和第二非易失性存储器元件中具有锁存的存储器元件，用于接收并永久地保持来自锁存的存储器元件的数字信号。 电力检测电路检测电力中断和电力启动，并将电力中断和电力启动的检测传送到多个集成的非易失性SRAM电路。 SRAM单元在检测到电源中断时将数字信号发送到第一和第二非易失性存储器元件。 在检测到功率启动时，每个非易失性静态随机存取存储器的SRAM单元接收来自第一和第二非易失性存储器元件的数字信号。

公开(公告)号：US20060005226A1

公开(公告)日：2006-01-05

申请号：US11126821

申请日：2005-05-10

申请人： Peter Lee

发明人： Peter Lee

IPC分类号： H04N7/16

CPC分类号： G11B27/105 ,  G06F16/178 ,  G06F16/435 ,  G11B27/10

摘要： A system for synchronizing a portable media player for downloading of content to said player and playing the downloaded content on the player including profile synchronizing means associated with the player for synchronizing content downloaded to said player related to the profile of the user of the player.

摘要翻译： 一种用于将便携式媒体播放器用于下载内容到所述播放器并且播放所述播放器上的下载内容的系统，其包括与所述播放器相关联的与所述播放器相关联的与所述播放器的用户的简档相关的下载的内容的简档同步装置。

公开(公告)号：US20050243503A1

公开(公告)日：2005-11-03

申请号：US10836344

申请日：2004-05-03

申请人： Kenneth Robertson ,  Peter Lee

发明人： Kenneth Robertson ,  Peter Lee

IPC分类号： G06F1/16 ,  G06F1/18 ,  G11B33/02 ,  G11B33/12

CPC分类号： G06F1/1632 ,  G06F1/184 ,  G06F1/187 ,  G11B33/022 ,  G11B33/122 ,  G11B33/124

摘要： An expansion module usable as an internal and external device is described. The module defines an interior volume, a recess for receiving a retaining latch external to the module for retaining the module positioned with respect to an expansion module sleeve, and at least two throughholes to the module interior and an alignment receptacle at one end of the module. The module includes a latch release attached to the module for expelling a retained latch from the recess, and an interface device positioned in the module interior volume, and receiving a) a standard data connector via one of the at least two throughholes and b) a power connector via another of the at least two throughholes, and including one or more expansion device connectors internal to the module interior volume for providing at least one of data signals and power received from the standard data connector and the power connector to an expansion device.

摘要翻译： 描述可用作内部和外部设备的扩展模块。 模块限定内部容积，用于接收模块外部的保持闩锁的凹部，用于保持相对于扩展模块套筒定位的模块，以及至少两个通孔到模块内部，以及在模块的一端处的对准插座 。 模块包括附接到模块的闩锁释放件，用于将保持的闩锁从凹部排出，以及定位在模块内部体积中的接口装置，以及经由至少两个通孔中的一个接收a）标准数据连接器，以及b） 电源连接器，并且包括模块内部容积内部的一个或多个扩展装置连接器，用于将数据信号和从标准数据连接器和电源连接器接收的功率中的至少一个提供给扩展装置。

公开(公告)号：US20050144706A1

公开(公告)日：2005-07-07

申请号：US10748907

申请日：2003-12-30

申请人： David Taylor ,  Peter Lee ,  Christopher Henderson

发明人： David Taylor ,  Peter Lee ,  Christopher Henderson

IPC分类号： A62B9/04 ,  A62B25/00 ,  A41F3/02 ,  A41F9/00 ,  A41F15/00

CPC分类号： A62B25/00

摘要： An anatomically fitted belt is used for carrying one or more waist-mounted respiratory protection components. The belt includes a main belt portion and a belt buckle portion. The main belt portion includes a back section, a left side section, a right side section, a left connective section between the back section and the left side section, and a right connective section between the back section and the right side section. The back section is wider than the other sections of the main belt portion. The main belt portion has a generally conical shape to be secured around a user's pelvic girdle and to align the respiratory component over the lumbar region of the user's spine to distribute a weight of the respiratory component. The belt buckle portion includes a right piece connected to the right side section of the main belt portion and a left piece connected to the left side section of the main belt portion.

摘要翻译： 解剖安装的皮带用于承载一个或多个腰部安装的呼吸保护部件。 带包括主带部分和带扣部分。 主带部分包括后部，左侧部分，右侧部分，后部部分和左侧部分之间的左连接部分以及后部部分和右侧部分之间的右连接部分。 后部比主带部分的其它部分宽。 主带部分具有大致圆锥形的形状，以固定在使用者的骨盆腰围周围并使呼吸部件对准使用者脊椎的腰部区域以分配呼吸部件的重量。 带扣部分包括连接到主带部分的右侧部分的右部件和连接到主带部分的左侧部分的左件。

公开(公告)号：US20050141298A1

公开(公告)日：2005-06-30

申请号：US11011306

申请日：2004-12-14

申请人： Peter Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

发明人： Peter Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

IPC分类号： G11C16/04 ,  G11C16/14 ,  H01L21/8247 ,  H01L27/115 ,  G11C5/00

CPC分类号： H01L27/115 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3445 ,  G11C2216/18 ,  G11C2216/22 ,  H01L27/11521 ,  H01L27/11524

摘要： A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

公开(公告)号：US20050130222A1

公开(公告)日：2005-06-16

申请号：US10479296

申请日：2002-05-24

申请人： Peter Lee

发明人： Peter Lee

IPC分类号： G01N27/62 ,  B01D59/44 ,  C12M1/34 ,  G01N1/00 ,  G01N1/36 ,  G01N33/53 ,  H01J49/04 ,  H01J49/16

CPC分类号： H01J49/0418 ,  G01N1/405

摘要： A novel Matrix-Assisted Laser Desorption/Ionization Mass Spectrometry (MALDI-MS) sample support plate is described. The plate comprises a top sample presentation surface and a lower surface, wherein the top sample presentation surface comprises at least one aperture for receiving a sample. The aperture extends through and between the top sample presentation surface and the bottom surface, and contains a porous material that retains and concentrates at the target spot analyte and matrix molecules contained in the sample on the surface of the aperture. Methods for making and using the sample support plate in conventional and automated MALDI-MS are also described.

摘要翻译： 描述了一种新型的矩阵辅助激光解吸/电离质谱（MALDI-MS）样品支撑板。 板包括顶部样品呈现表面和下表面，其中顶部样品呈现表面包括用于接收样品的至少一个孔。 孔径延伸穿过顶部样品呈现表面和底部表面之间并且包含多孔材料，其保留并集中在靶点分析物和包含在孔的表面上的样品中的基质分子。 还描述了在常规和自动化的MALDI-MS中制备和使用样品支持板的方法。

公开(公告)号：US20050128805A1

公开(公告)日：2005-06-16

申请号：US11036961

申请日：2005-01-14

申请人： Peter Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

发明人： Peter Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L27/115

CPC分类号： H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

公开(公告)号：US20050042885A1

公开(公告)日：2005-02-24

申请号：US10645675

申请日：2003-08-20

申请人： Lihua Li ,  Tsutomu Tanaka ,  Tzu-Fang Huang ,  Li-Qun Xia ,  Dian Sugiarto ,  Visweswaren Sivaramakrishnan ,  Peter Lee ,  Mario Silvetti

发明人： Lihua Li ,  Tsutomu Tanaka ,  Tzu-Fang Huang ,  Li-Qun Xia ,  Dian Sugiarto ,  Visweswaren Sivaramakrishnan ,  Peter Lee ,  Mario Silvetti

IPC分类号： C23C16/40 ,  C23C16/509 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L21/31 ,  H01L21/469

CPC分类号： C23C16/5096 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/76801

摘要： A method for depositing an organosilicate layer on a substrate includes varying one or more processing conditions during a process sequence for depositing an organosilicate layer from a gas mixture comprising an organosilicon compound in the presence of RF power in a processing chamber. In one aspect, the distance between the substrate and a gas distribution manifold in the processing chamber is varied during processing. Preferably, the method of depositing an organosilicate layer minimizes plasma-induced damage to the substrate.

公开(公告)号：US20050021594A1

公开(公告)日：2005-01-27

申请号：US10728732

申请日：2003-12-05

申请人： James Bernardin ,  Peter Lee

发明人： James Bernardin ,  Peter Lee

IPC分类号： G06F9/50 ,  G06F15/16

CPC分类号： G06F9/505 ,  G06F2209/503 ,  Y10S707/99932

摘要： A service-oriented framework allows client applications to access computational services hosted on a distributed computing grid. Services facilitate remote, parallel execution of code in a way that is scalable, fault-tolerant, dynamic and language-independent. Services can be written in a variety of languages, and do not need to be compiled or linked with vendor-supplied code. A client written in one language can invoke a Service written in another. A benefit of the invention over traditional approaches is that it virtualizes the Service. Rather than send a request directly to the remote machine hosting the Service, a client request is sent to a manager, which enqueues it until an Engine is available. The first Engine to dequeue the request hosts the Service. This mechanism, in which a single virtual Service instance (the client-side object) is implemented by one or more physical instances (Engine processes), provides for fault tolerance and essentially unlimited scalability.

摘要翻译： 面向服务的框架允许客户端应用程序访问托管在分布式计算网格上的计算服务。 服务可以以可扩展，容错，动态和语言无关的方式实现代码的远程并行执行。 服务可以用各种语言编写，不需要编译或链接供应商提供的代码。 以一种语言编写的客户端可以调用另一种语言编写的服务。 与传统方法相比，本发明的优点在于它虚拟化了服务。 而不是直接向托管服务的远程机器发送请求，客户端请求将发送到管理器，管理员将排队，直到引擎可用。 出现该请求的第一个引擎托管服务。 单个虚拟服务实例（客户端对象）由一个或多个物理实例（引擎进程）实现的这种机制提供了容错和基本上无限的可扩展性。

公开(公告)号：US06839278B1

公开(公告)日：2005-01-04

申请号：US10353584

申请日：2003-01-29

申请人： Peter Lee ,  Fu-Chang Hsu

发明人： Peter Lee ,  Fu-Chang Hsu

IPC分类号： G11C11/00 ,  G11C16/04 ,  G11C17/12 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/112 ,  H01L27/115

CPC分类号： H01L27/11521 ,  G11C11/005 ,  G11C16/0491 ,  G11C17/126 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11253 ,  H01L27/11293 ,  H01L27/115 ,  H01L27/11526

摘要： A memory device is achieved. The memory device comprises an array of Flash cells and mask ROM cells in a common substrate. Each Flash cell comprises a floating gate, a control gate, a source, a drain, and a channel. Each mask ROM cell comprises a gate, a source, a drain, and a channel. Each source of the mask ROM cells is shared with one Flash cell source. Each electrode of each mask ROM cell gate is coupled to at least one Flash cell control gate. The mask ROM cell gate electrodes comprise a common layer with electrodes of the Flash cell control gates. The mask ROM cells lie in spaces between the Flash cells in the array.

摘要翻译： 实现了存储器件。 存储器件包括在公共衬底中的闪存单元阵列和掩模ROM单元阵列。 每个闪存单元包括浮动栅极，控制栅极，源极，漏极和沟道。 每个掩模ROM单元包括栅极，源极，漏极和沟道。 掩模ROM单元的每个源都与一个闪存单元源共享。 每个掩模ROM单元门的每个电极耦合到至少一个闪存单元控制门。 掩模ROM单元栅电极包括具有闪存单元控制栅极的电极的公共层。 掩模ROM单元位于阵列中的闪存单元之间的空格中。