公开(公告)号：US08541833B2

公开(公告)日：2013-09-24

申请号：US13082679

申请日：2011-04-08

申请人： Hans-Joachim Schulze ,  Anton Mauder ,  Helmut Strack ,  Franz Hirler

发明人： Hans-Joachim Schulze ,  Anton Mauder ,  Helmut Strack ,  Franz Hirler

IPC分类号： H01L29/66 ,  H01L21/70

CPC分类号： H01L21/823487 ,  H01L27/0694 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor component includes a sequence of layers, the sequence of layers including a first insulator layer, a first semiconductor layer disposed on the first insulator layer, a second insulator layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the second insulator layer. The semiconductor component also includes a plurality of devices at least partly formed in the first semiconductor layer. A first one of the plurality of devices is a power transistor formed in a first region of the first semiconductor layer and a first region of the second semiconductor layer. The first region of the first and second semiconductor layers are in electrical contact with one another through a first opening in the second insulator layer.

摘要翻译： 半导体部件包括一层层，所述层序列包括第一绝缘体层，设置在第一绝缘体层上的第一半导体层，设置在第一半导体层上的第二绝缘体层，以及设置在第二绝缘体层上的第二半导体层 绝缘体层。 半导体部件还包括至少部分地形成在第一半导体层中的多个器件。 多个器件中的第一个是在第一半导体层的第一区域和第二半导体层的第一区域中形成的功率晶体管。 第一和第二半导体层的第一区域通过第二绝缘体层中的第一开口彼此电接触。

公开(公告)号：US08530300B2

公开(公告)日：2013-09-10

申请号：US12842488

申请日：2010-07-23

申请人： Joachim Weyers ,  Armin Willmeroth ,  Anton Mauder ,  Franz Hirler

发明人： Joachim Weyers ,  Armin Willmeroth ,  Anton Mauder ,  Franz Hirler

IPC分类号： H01L21/8238

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/8613 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method of forming a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type, and a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type.

摘要翻译： 公开了一种形成具有第一掺杂类型的漂移区和第二掺杂型的补偿区的半导体器件的方法，以及具有第一掺杂类型的漂移区和第二掺杂类型的补偿区的半导体器件。

公开(公告)号：US20130221427A1

公开(公告)日：2013-08-29

申请号：US13404161

申请日：2012-02-24

申请人： Ralf Siemieniec ,  Oliver Blank ,  Anton Mauder ,  Franz Hirler

发明人： Ralf Siemieniec ,  Oliver Blank ,  Anton Mauder ,  Franz Hirler

IPC分类号： H01L29/78 ,  H01L21/04

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device includes a first contact in low Ohmic contact with a source region of the device and a first portion of a body region of the device formed in an active area of the device, and a second contact in low Ohmic contact with a second portion of the body region formed in a peripheral area of the device. The minimum width of the second contact at a first surface of the device is larger than the minimum width of the first contact at the first surface so that maximum current density during commutating the semiconductor device is reduced and thus the risk of device damage during hard commutating is also reduced.

摘要翻译： 半导体器件包括与器件的源极区域的低欧姆接触的第一接触和形成在器件的有源区域中的器件的体区的第一部分，以及与第二部分的低欧姆接触的第二接触 形成在装置的周边区域中的身体区域。 器件第一表面处的第二触点的最小宽度大于第一表面处的第一接触的最小宽度，使得在半导体器件的整流期间的最大电流密度降低，并且因此在硬整流期间器件损坏的风险 也减少了。

公开(公告)号：US08502315B2

公开(公告)日：2013-08-06

申请号：US13463243

申请日：2012-05-03

申请人： Anton Mauder ,  Rudolf Berger ,  Franz Hirler ,  Ralf Siemieniec ,  Hans-Joachim Schulze

发明人： Anton Mauder ,  Rudolf Berger ,  Franz Hirler ,  Ralf Siemieniec ,  Hans-Joachim Schulze

IPC分类号： H01L29/78

CPC分类号： H01L29/66719 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/408 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone.

摘要翻译： 半导体器件包括源极，漏极和被配置为选择性地使电流在源极和漏极之间通过的栅极。 半导体器件包括源极和漏极之间的漂移区和邻近漂移区的第一场板。 半导体器件包括将第一场板与漂移区电隔离的电介质层，并且电介质层内的电荷接近靠近漂移区的电介质层的界面。

公开(公告)号：US08435853B2

公开(公告)日：2013-05-07

申请号：US12871038

申请日：2010-08-30

申请人： Franz Hirler ,  Anton Mauder ,  Frank Pfirsch ,  Hans-Joachim Schulze

发明人： Franz Hirler ,  Anton Mauder ,  Frank Pfirsch ,  Hans-Joachim Schulze

IPC分类号： H01L21/8234

CPC分类号： H01L29/66143 ,  H01L21/823487 ,  H01L29/0626 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/6609 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7813

摘要： A method for forming a field effect power semiconductor is provided. The method includes providing a semiconductor body, a conductive region arranged next to a main surface of the semiconductor body, and an insulating layer arranged on the main horizontal surface. A narrow trench is etched through the insulating layer to expose the conductive region. A polycrystalline semiconductor layer is deposited and a vertical poly-diode structure is formed. The polycrystalline semiconductor layer has a minimum vertical thickness of at least half of the maximum horizontal extension of the narrow trench. A polycrystalline region which forms at least a part of a vertical poly-diode structure is formed in the narrow trench by maskless back-etching of the polycrystalline semiconductor layer. Further, a semiconductor device with a trench poly-diode is provided.

摘要翻译： 提供了一种用于形成场效应功率半导体的方法。 该方法包括提供半导体本体，邻近半导体主体的主表面布置的导电区域和布置在主水平表面上的绝缘层。 通过绝缘层蚀刻窄沟槽以暴露导电区域。 沉积多晶半导体层并形成垂直多晶二极管结构。 多晶半导体层的最小垂直厚度为窄沟槽的最大水平延伸的至少一半。 通过多晶半导体层的无掩模背面蚀刻，在窄沟槽中形成形成垂直多晶二极管结构的至少一部分的多晶区域。 此外，提供了具有沟槽多晶二极管的半导体器件。

公开(公告)号：US20130005099A1

公开(公告)日：2013-01-03

申请号：US13537374

申请日：2012-06-29

申请人： Hans Weber ,  Franz Hirler ,  Andreas Meiser ,  Anton Mauder ,  Kurt Sorschag ,  Stefan Gamerith ,  Roman Knoefler

发明人： Hans Weber ,  Franz Hirler ,  Andreas Meiser ,  Anton Mauder ,  Kurt Sorschag ,  Stefan Gamerith ,  Roman Knoefler

IPC分类号： H01L21/336 ,  H01L21/20

CPC分类号： H01L29/7802 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/0629 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7828

摘要： A semiconductor device with a dielectric layer is produced by providing a semiconductor body with a first trench extending into the semiconductor body, the first trench having a bottom and a sidewall. A first dielectric layer is formed on the sidewall in a lower portion of the first trench and a first plug is formed in the lower portion of the first trench so as to cover the first dielectric layer. The first plug leaves an upper portion of the sidewall uncovered. A sacrificial layer is formed on the sidewall in the upper portion of the first trench and a second plug is formed in the upper portion of the first trench. The sacrificial layer is removed so as to form a second trench having sidewalls and a bottom. A second dielectric layer is formed in the second trench and extends to the first dielectric layer.

摘要翻译： 具有电介质层的半导体器件通过向半导体本体提供延伸到半导体本体中的第一沟槽，第一沟槽具有底部和侧壁来制造。 第一电介质层形成在第一沟槽的下部的侧壁上，第一插塞形成在第一沟槽的下部，以覆盖第一电介质层。 第一个塞子留下未覆盖的侧壁的上部。 牺牲层形成在第一沟槽的上部的侧壁上，第二插塞形成在第一沟槽的上部。 除去牺牲层以形成具有侧壁和底部的第二沟槽。 第二介电层形成在第二沟槽中并延伸到第一介电层。

公开(公告)号：US07977737B2

公开(公告)日：2011-07-12

申请号：US12043429

申请日：2008-03-06

申请人： Armin Willmeroth ,  Winfried Kaindl ,  Carolin Tolksdorf ,  Anton Mauder ,  Holger Kapels ,  Gerald Deboy ,  Franz Hirler

发明人： Armin Willmeroth ,  Winfried Kaindl ,  Carolin Tolksdorf ,  Anton Mauder ,  Holger Kapels ,  Gerald Deboy ,  Franz Hirler

IPC分类号： H01L29/66 ,  H01L21/337

CPC分类号： H01L27/0733 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device with inherent capacitances and method for its production. The semiconductor device has an inherent feedback capacitance between a control electrode and a first electrode. In addition, the semiconductor device has an inherent drain-source capacitance between the first electrode and a second electrode. At least one monolithically integrated additional capacitance is connected in parallel to the inherent feedback capacitance or in parallel to the inherent drain-source capacitance. The additional capacitance comprises a first capacitor surface and a second capacitor surface opposite the first capacitor surface. The capacitor surfaces are structured conductive layers of the semiconductor device on a front side of the semiconductor body, between which a dielectric layer is located and which form at least one additional capacitor.

摘要翻译： 具有固有电容的半导体器件及其制造方法。 半导体器件在控制电极和第一电极之间具有固有的反馈电容。 此外，半导体器件在第一电极和第二电极之间具有固有的漏极 - 源极电容。 至少一个单片集成附加电容与固有反馈电容并联连接，或与固有漏 - 源电容并联连接。 附加电容包括与第一电容器表面相对的第一电容器表面和第二电容器表面。 电容器表面是半导体器件的前侧上的半导体器件的结构化导电层，介电层位于其之间，并形成至少一个附加电容器。

公开(公告)号：US07943449B2

公开(公告)日：2011-05-17

申请号：US12241828

申请日：2008-09-30

申请人： Anton Mauder ,  Stefan Sedlmaier ,  Ralf Erichsen ,  Hans Weber ,  Oliver Haeberlen ,  Franz Hirler

发明人： Anton Mauder ,  Stefan Sedlmaier ,  Ralf Erichsen ,  Hans Weber ,  Oliver Haeberlen ,  Franz Hirler

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7813 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7804

摘要： A method for producing a semiconductor structure and a semiconductor component are described.

摘要翻译： 对半导体结构体及半导体部件的制造方法进行说明。

公开(公告)号：US20100258801A1

公开(公告)日：2010-10-14

申请号：US12421346

申请日：2009-04-09

申请人： Joachim Weyers ,  Anton Mauder ,  Franz Hirler ,  Paul Kuepper

发明人： Joachim Weyers ,  Anton Mauder ,  Franz Hirler ,  Paul Kuepper

IPC分类号： H01L29/786 ,  H01L29/78

CPC分类号： H01L29/872 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/402 ,  H01L29/405 ,  H01L29/42384 ,  H01L29/7393 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/78609 ,  H01L29/78624 ,  H01L29/78645 ,  H01L29/78648

摘要： A semiconductor component including a lateral transistor component is disclosed. One embodiment provides an electrically insulating carrier layer. On the carrier layer a first and a second semiconductor layer are arranged on above another and are separated from another by a dielectric layer and from which at least the first semiconductor layer includes a polycrystalline semiconductor material, an amorphous semiconductor material or an organic semiconductor material. In the first semiconductor layer: a source zone, a body zone, a drift zone and a drain zone are provided. In the second semiconductor layer; a drift control zone is arranged adjacent to the drift zone, including a control terminal at a first lateral end for applying a control potential, and is coupled to the drain zone via a rectifying element at a second lateral end. A gate electrode is arranged adjacent to the body zone and is dielectrically insulated from the body zone by a gate dielectric layer.

摘要翻译： 公开了一种包括横向晶体管元件的半导体元件。 一个实施例提供电绝缘载体层。 在载体层上，第一和第二半导体层被布置在另一个之上，并且通过电介质层与另一个隔离，并且至少第一半导体层至少包括多晶半导体材料，非晶半导体材料或有机半导体材料。 在第一半导体层中提供源极区，体区，漂移区和漏区。 在第二半导体层中; 漂移控制区被布置成与漂移区相邻，包括用于施加控制电位的第一横向端的控制端，并且在第二横向端通过整流元件耦合到排水区。 栅极电极被布置成与身体区域相邻并且通过栅极介电层与身体区域介电绝缘。

公开(公告)号：US07709891B2

公开(公告)日：2010-05-04

申请号：US12019271

申请日：2008-01-24

申请人： Anton Mauder ,  Stefan Sedlmaier ,  Franz Hirler ,  Armin Willmeroth ,  Gerhard Noebauer

发明人： Anton Mauder ,  Stefan Sedlmaier ,  Franz Hirler ,  Armin Willmeroth ,  Gerhard Noebauer

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/7803 ,  H01L29/7831 ,  H03K17/04206 ,  H03K17/063 ,  H03K17/567

摘要： A component arrangement. One embodiment includes a power semiconductor component having a drift zone arranged between a first and a second component zone. A drift control zone is arranged adjacent to the drift zone and is dielectrically insulated from the drift zone by a dielectric layer. A capacitive storage arrangement is coupled to the drift control zone. A charging circuit is coupled between the first component zone and the capacitive storage arrangement.

摘要翻译： 组件安排。 一个实施例包括具有布置在第一和第二组件区之间的漂移区的功率半导体组件。 漂移控制区域布置成与漂移区相邻并且通过介电层与漂移区介电绝缘。 电容存储装置耦合到漂移控制区。 充电电路耦合在第一组件区域和电容存储装置之间。