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    Semiconductor device having a strained raised source/drain
    55.
    发明授权
    Semiconductor device having a strained raised source/drain 失效
    具有应变升高源极/漏极的半导体器件

    公开(公告)号：US07115955B2

    公开(公告)日：2006-10-03

    申请号：US10710738

    申请日：2004-07-30

    申请人： Brian Messenger ,  Renee T. Mo ,  Dominic J. Schepis

    发明人： Brian Messenger ,  Renee T. Mo ,  Dominic J. Schepis

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/66742 ,  H01L29/7842 ,  H01L29/78687

    摘要： A manufacturable way to recess silicon that employs an end point detection method for the recess etch and allows tight tolerances on the recess is described for fabricating a strained raised source/drain layer. The method includes forming a monolayer comprising oxygen and carbon on a surface of a doped semiconductor substrate; forming an epi Si layer atop the doped semiconductor substrate; forming at least one gate region on the epi Si layer; selectively etching exposed portions of the epi layer, not protected by the gate region, stopping on and exposing the doped semiconductor substrate using end point detection; and forming a strained SiGe layer on the exposed doped semiconductor substrate. The strained SiGe layer serves as a raised layer in which source/drain diffusion regions can be subsequently formed.

    摘要翻译： 为了制造应变升高的源极/漏极层，描述了用于凹陷蚀刻采用端点检测方法以及允许在凹槽上的紧密公差的硅的可制造方法。 该方法包括在掺杂的半导体衬底的表面上形成包含氧和碳的单层; 在掺杂半导体衬底的顶部形成外延Si层; 在外延Si层上形成至少一个栅极区; 选择性地蚀刻未被栅极区域保护的外延层的暴露部分，使用端点检测停止并暴露掺杂半导体衬底; 以及在所述暴露的掺杂半导体衬底上形成应变SiGe层。 应变SiGe层用作可以随后形成源/漏扩散区的凸起层。

    Method for monitoring lateral encroachment of spacer process on a CD SEM
    56.
    发明授权
    Method for monitoring lateral encroachment of spacer process on a CD SEM 失效

    公开(公告)号：US07105398B2

    公开(公告)日：2006-09-12

    申请号：US10942303

    申请日：2004-09-16

    申请人： Bachir Dirahoui ,  Renee T. Mo ,  Ravikumar Ramachandran ,  Eric P. Solecky

    发明人： Bachir Dirahoui ,  Renee T. Mo ,  Ravikumar Ramachandran ,  Eric P. Solecky

    IPC分类号： H01L21/8238

    CPC分类号： H01L22/12

    摘要： A process implementing steps for determining encroachment of a spacer structure in a semiconductor device having thick and thin spacer regions, including a transition region formed therebetween. The method steps comprise: obtaining a line width roughness (LWR) measurement at at least one location along each thick, thin and transition spacer regions; determining a threshold LWR measurement value based on the LWR measurements; defining a region of interest (ROI) and obtaining a further LWR measurement in the ROI; comparing the LWR measurement in the ROI against the threshold LWR measurement value; and, notifying a user that either encroachment of the spacer structure is present when the LWR measurement in the ROI is below the threshold LWR measurement value, or that no encroachment of the spacer structure is present when the LWR measurement in the ROI is above the threshold LWR measurement value.

    Ultra-thin body super-steep retrograde well (SSRW) FET devices
    58.
    发明授权
    Ultra-thin body super-steep retrograde well (SSRW) FET devices 有权
    超薄体超陡逆行井（SSRW）FET器件

    公开(公告)号：US07002214B1

    公开(公告)日：2006-02-21

    申请号：US10710736

    申请日：2004-07-30

    申请人： Diane C. Boyd ,  Judson R. Holt ,  MeiKei Ieong ,  Renee T. Mo ,  Zhibin Ren ,  Ghavam G. Shahidi

    发明人： Diane C. Boyd ,  Judson R. Holt ,  MeiKei Ieong ,  Renee T. Mo ,  Zhibin Ren ,  Ghavam G. Shahidi

    IPC分类号： H01L27/12

    CPC分类号： H01L27/1203 ,  H01L21/76283 ,  H01L21/823892 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78696

    摘要： A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.

    摘要翻译： 超陡逆行井场效应晶体管器件的制造方法从形成在衬底上的SOI层开始。 掩埋氧化层。 使SOI层变薄以形成超薄SOI层。 形成将SOI层分离成N和P接地平面区域的隔离沟槽。 用高水平的N型和P型掺杂剂掺杂由SOI层形成的N和P接地平面区域。 在N和P接地平面区域之上形成半导体沟道区。 在沟道区域上方形成FET源极和漏极区域以及栅极电极堆叠。 可选地，在SOI接地平面区域和沟道区域之间形成扩散延迟层。

    High-k/metal gate transistor with L-shaped gate encapsulation layer
    60.
    发明授权
    High-k/metal gate transistor with L-shaped gate encapsulation layer 有权
    具有L形栅极封装层的高k /金属栅极晶体管

    公开(公告)号：US09252018B2

    公开(公告)日：2016-02-02

    申请号：US13571977

    申请日：2012-08-10

    申请人： Renee T. Mo ,  Wesley C. Natzle ,  Vijay Narayanan ,  Jeffrey W. Sleight

    发明人： Renee T. Mo ,  Wesley C. Natzle ,  Vijay Narayanan ,  Jeffrey W. Sleight

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

    CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

    摘要： A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack.

    摘要翻译： 提供晶体管，其包括具有源极区和漏极区的硅层，设置在源极区和漏极区之间的硅层上的栅极堆叠，设置在栅极堆叠的侧壁上的L形栅极封装层，以及 设置在栅极封装层的水平部分上方并且与栅极封装层的垂直部分相邻的间隔物。 栅堆叠具有第一层高介电常数材料，第二层包括金属或金属合金，以及第三层包括硅或多晶硅。 栅极封装层具有覆盖栅极堆叠的第一，第二和第三层的侧壁的垂直部分和覆盖与栅极叠层相邻的硅层的一部分的水平部分。