公开(公告)号：US20180061839A1

公开(公告)日：2018-03-01

申请号：US15252995

申请日：2016-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Jürgen Thees

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L27/12 ,  H01L29/66 ,  H01L21/762 ,  H01L21/285 ,  H01L21/84 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165

CPC classification number: H01L27/10811 ,  H01L21/28518 ,  H01L21/76283 ,  H01L21/76897 ,  H01L21/84 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/1203 ,  H01L28/82 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7838 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device structure is disclosed including a semiconductor-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor layer, a substrate material and a buried insulating material layer positioned between the semiconductor layer and the substrate material, a trench isolation structure positioned in at least a portion of the SOI substrate, the trench isolation structure defining a first region in the SOI substrate, and a capacitor device formed in the first region, the capacitor device comprising a first electrode formed by a conductive layer portion formed in the first region on the buried insulating material layer, the conductive layer portion at least partially replacing the semiconductor layer in the first region, a second electrode formed over the first electrode, and an insulating material formed between the first electrode and the second electrode.

公开(公告)号：US09806170B1

公开(公告)日：2017-10-31

申请号：US15151550

申请日：2016-05-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert Mulfinger ,  Ryan Sporer ,  Rick J. Carter ,  Peter Baars ,  Hans-Jürgen Thees ,  Jan Höntschel

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/7838

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

公开(公告)号：US20170162557A1

公开(公告)日：2017-06-08

申请号：US14958150

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Juergen Faul

IPC: H01L27/02 ,  H01L29/66 ,  H01L21/84 ,  H01L29/417 ,  H01L27/12 ,  H01L27/07 ,  H01L49/02

CPC classification number: H01L27/0222 ,  G05F3/205 ,  H01L27/1203 ,  H01L27/13 ,  H01L28/40 ,  H01L29/665 ,  H01L29/945

Abstract: A semiconductor device is provided including a fully depleted silicon-on-insulator (FDSOI) substrate and a charge pump device, wherein the FDSOI substrate comprises a semiconductor bulk substrate, and the charge pump device comprises a transistor device formed in and on the FDSOI substrate, and a trench capacitor formed in the semiconductor bulk substrate and electrically connected to the transistor device. A semiconductor device is further provided including a semiconductor bulk substrate, a first transistor device comprising a first source/drain region, a second transistor device comprising a second source/drain region, a first trench capacitor comprising a first inner capacitor electrode and a first outer capacitor electrode, and a second trench capacitor comprising a second inner capacitor electrode and a second outer capacitor electrode, wherein the first inner capacitor electrode is connected to the first source/drain region and the second inner capacitor electrode is connected to the second source/drain region.

公开(公告)号：US09666589B1

公开(公告)日：2017-05-30

申请号：US15075352

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Juergen Faul

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/11541 ,  H01L27/11521 ,  H01L27/11536

CPC classification number: H01L29/66825 ,  H01L21/266 ,  H01L21/7684 ,  H01L21/76883 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0886 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/788 ,  H01L29/7881

Abstract: A method of manufacturing a semiconductor device is provided including providing a semiconductor substrate, forming a first plurality of semiconductor fins in a logic area of the semiconductor substrate, forming a second plurality of semiconductor fins in a memory area of the semiconductor substrate, forming an insulating layer between the fins of the first plurality of semiconductor fins and between the fins of the second plurality of semiconductor fins, forming an electrode layer over the first and second pluralities of semiconductor fins and the insulating layer, forming gates over semiconductor fins of the first plurality of semiconductor fins in the logic area from the gate electrode layer, and forming sense gates and control gates between semiconductor fins of the second plurality of semiconductor fins in the logic area from the gate electrode layer.

公开(公告)号：US09634088B1

公开(公告)日：2017-04-25

申请号：US15185267

申请日：2016-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0922 ,  H01L29/0642 ,  H01L29/16 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78684

Abstract: A method of forming a semiconductor device is disclosed including providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer, and forming a transistor device on the silicon-on-insulator substrate including providing a gate structure on the semiconductor layer having a gate electrode and a first cap layer on the gate electrode, growing an oxide liner on the transistor device having a first part covering the gate structure and a second part covering the semiconductor layer, forming a second cap layer on the oxide liner, at least partially removing the second part of the oxide liner underneath the second cap layer and the first part of the oxide liner, and epitaxially forming raised source/drain regions on the semiconductor layer.

公开(公告)号：US09553046B2

公开(公告)日：2017-01-24

申请号：US14718502

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC: H01L21/331 ,  H01L23/525 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L23/5256 ,  H01L21/84 ,  H01L27/1203

Abstract: A method of forming a semiconductor device comprising a fuse is provided including providing a semiconductor-on-insulator (SOI) structure comprising an insulating layer and a semiconductor layer formed on the insulating layer, forming raised semiconductor regions on the semiconductor layer adjacent to a central portion of the semiconductor layer and performing a silicidation process of the central portion of the semiconductor layer and the raised semiconductor regions to form a silicided semiconductor layer and silicided raised semiconductor regions.

Abstract translation: 提供一种形成包括熔丝的半导体器件的方法，包括：提供绝缘层上的绝缘体上半导体结构（SOI）结构和形成在绝缘层上的半导体层，在与中心相邻的半导体层上形成凸起的半导体区域 并且对半导体层的中心部分和凸起的半导体区域进行硅化处理，以形成硅化半导体层和硅化凸起的半导体区域。

公开(公告)号：US09502564B2

公开(公告)日：2016-11-22

申请号：US15164374

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC: H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78639 ,  H01L29/78654

Abstract: A semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and a buried insulating material region disposed in the active region under the gate structure. The buried insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth of the active region. The source/drain regions have a depth greater than a top surface of the buried insulating material region.

Abstract translation: 半导体器件包括形成在半导体衬底中的有源区，设置在有源区上的栅极结构，形成在与栅结构对准的有源区中的源极/漏极区，以及设置在有源区内的掩埋绝缘材料区 门结构。 掩埋绝缘材料区域被有源区域包围，并且沿着有源区域的深度与栅极结构下方的有源区域中的沟道区域相邻。 源/漏区具有大于掩埋绝缘材料区的顶表面的深度。

公开(公告)号：US20160315016A1

公开(公告)日：2016-10-27

申请号：US14695232

申请日：2015-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/76264 ,  H01L21/84 ,  H01L21/845 ,  H01L27/127 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/78648 ,  H01L29/78684

Abstract: A method of forming a semiconductor device is provided including providing a semiconductor-on-insulator (SOI) wafer comprising a first semiconductor layer comprising a first material component and formed on a buried oxide (BOX) layer, and forming a channel region of a P-channel transistor device, including forming a second semiconductor layer only over a first portion of the first semiconductor layer, wherein the second semiconductor layer comprises the first material component and a second material component different from the first material component, forming an opening in the first semiconductor layer outside the first portion and subsequently performing a thermal anneal to push the second material component from the second semiconductor layer into the first semiconductor layer.

Abstract translation: 提供一种形成半导体器件的方法，包括：提供绝缘体上半导体（SOI）晶片，其包括第一半导体层，其包含第一材料成分并形成在掩埋氧化物（BOX）层上，并形成P 通道晶体管器件，包括只在第一半导体层的第一部分上形成第二半导体层，其中第二半导体层包括第一材料成分和与第一材料成分不同的第二材料成分，在第一 半导体层，然后进行热退火，以将第二材料成分从第二半导体层推入第一半导体层。

公开(公告)号：US20160268431A1

公开(公告)日：2016-09-15

申请号：US15164374

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78639 ,  H01L29/78654

Abstract: A semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and a buried insulating material region disposed in the active region under the gate structure. The buried insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth of the active region. The source/drain regions have a depth greater than a top surface of the buried insulating material region.

Abstract translation: 半导体器件包括形成在半导体衬底中的有源区，设置在有源区上的栅极结构，形成在与栅结构对准的有源区中的源极/漏极区，以及设置在有源区内的掩埋绝缘材料区 门结构。 掩埋绝缘材料区域被有源区域包围，并且沿着有源区域的深度与栅极结构下方的有源区域中的沟道区域相邻。 源/漏区具有大于掩埋绝缘材料区的顶表面的深度。

公开(公告)号：US20160204128A1

公开(公告)日：2016-07-14

申请号：US14592069

申请日：2015-01-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Peter Moll ,  Jan Hoentschel

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/321 ,  H01L29/66 ,  H01L27/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/49 ,  H01L49/02 ,  H01L21/84 ,  H01L21/308

CPC classification number: H01L27/1207 ,  H01L21/308 ,  H01L21/3212 ,  H01L21/76224 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7838

Abstract: A method of forming a semiconductor device structure includes providing a substrate with a semiconductor-on-insulator (SOI) configuration, the SOI substrate comprising a semiconductor layer formed on a buried oxide (BOX) layer which is disposed on a semiconductor bulk substrate, forming trench isolation structures delineating a first region and a second region within the SOI substrate, removing the semiconductor layer and the BOX layer in the first region for exposing the semiconductor bulk substrate within the first region, forming a first semiconductor device with an electrode in and over the exposed semiconductor bulk substrate in the first region, forming a second semiconductor device in the second region, the second semiconductor device comprising a gate structure disposed over the semiconductor layer and the BOX layer in the second region, and performing a polishing process for defining a common height level to which the electrode and the gate structure substantially extend.

Abstract translation: 一种形成半导体器件结构的方法包括：提供具有绝缘体上半导体（SOI）结构的衬底，所述SOI衬底包括形成在半导体本体衬底上的掩埋氧化物（BOX）层上形成的半导体层，形成 描绘SOI衬底内的第一区域和第二区域的沟槽隔离结构，去除第一区域中的半导体层和BOX层，用于在第一区域内暴露半导体本体衬底，形成具有电极的第一半导体器件 在所述第一区域中暴露的半导体体基板，在所述第二区域中形成第二半导体器件，所述第二半导体器件包括设置在所述半导体层上的栅极结构和所述第二区域中的BOX层，以及执行用于定义 电极和栅极结构基本上延伸的公共高度电平。