公开(公告)号：US10388652B2

公开(公告)日：2019-08-20

申请号：US15811961

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yongiun Shi ,  Lei Sun ,  Laertis Economikos ,  Ruilong Xie ,  Lars Liebmann ,  Chanro Park ,  Daniel Chanemougame ,  Min Gyu Sung ,  Hsien-Ching Lo ,  Haiting Wang

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L27/02 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/027

Abstract: The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.

公开(公告)号：US10373877B1

公开(公告)日：2019-08-06

申请号：US15986390

申请日：2018-05-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Hui Zang ,  Wei Zhao ,  Yue Zhong ,  Guowei Xu ,  Laertis Economikos ,  Jerome Ciavatti ,  Scott Beasor

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84

Abstract: One illustrative method disclosed herein includes forming a plurality of transistors on a semiconductor substrate, wherein each of the transistors comprise source/drain epitaxial semiconductor material in the source/drain regions, a contact etch stop layer (CESL) positioned above the source/drain epitaxial semiconductor material and an insulating material positioned above the contact etch stop layer, and forming a plurality of contact isolation cavities by performing at least one etching process sequence, wherein the etching process sequence is adapted to sequentially remove the insulating material, the CESL and the source/drain epitaxial semiconductor material, and forming a contact isolation structure in each of the contact isolation cavities. In this example, the method also includes, after forming the contact isolation structures, removing the sacrificial gate structures so as to form a plurality of replacement gate cavities, and forming a final gate structure in each of the plurality of replacement gate cavities.

公开(公告)号：US20190097019A1

公开(公告)日：2019-03-28

申请号：US15712748

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Haiting Wang ,  David P. Brunco ,  Jiehui Shu ,  Shesh Mani Pandey ,  Jinping Liu ,  Scott Beasor

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/417 ,  H01L21/762

CPC classification number: H01L29/6681 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02664 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/41791 ,  H01L29/66795

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.

公开(公告)号：US10083874B1

公开(公告)日：2018-09-25

申请号：US15467536

申请日：2017-03-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong Yu ,  Zhenyu Hu ,  Haiting Wang

IPC: H01L21/311 ,  H01L21/302 ,  H01L21/461 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/8234 ,  H01L21/033 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/3065

Abstract: A method of manufacturing a FinFET structure involves forming gate cuts within a sacrificial gate layer prior to patterning and etching the sacrificial gate layer to form longitudinal sacrificial gate structures. By forming transverse cuts in the sacrificial gate layer before defining the sacrificial gate structures longitudinally, dimensional precision of the gate cuts at lower critical dimensions can be improved.

公开(公告)号：US09443771B1

公开(公告)日：2016-09-13

申请号：US14935676

申请日：2015-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanping Shen ,  Min-hwa Chi ,  Ashish Kumar Jha ,  Haiting Wang

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823828 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/32155 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method of removing RMG sidewall layers, and the resulting device are provided. Embodiments include forming a TiN layer in nFET and pFET RMG trenches; forming an a-Si layer over the TiN layer; implanting O2 vertically in the a-Si layer; removing the a-Si layer and TiN layer from the side surfaces of the RMG trenches followed by the a-Si layer from the bottom surfaces; forming a TiN layer in the RMG trenches; forming a a-Si layer over the TiN layer; implanting O2 vertically in the a-Si layer; removing the a-Si layer and TiN layer from the side surfaces of the RMG trenches, the a-Si layer from the bottom surfaces, and a remainder of the TiN layer from only the nFET RMG trench; forming a Ti layer in the RMG trenches; implanting Al or C in the Ti layer vertically and annealing; and filling the RMG trenches with Al or W.

Abstract translation: 提供去除RMG侧壁层的方法，并且提供所得到的装置。 实施例包括在nFET和pFET RMG沟槽中形成TiN层; 在TiN层上形成a-Si层; 在a-Si层中垂直注入O2; 从RMG沟槽的侧表面除去a-Si层和TiN层，然后从底表面除去a-Si层; 在RMG沟槽中形成TiN层; 在TiN层上形成a-Si层; 在a-Si层中垂直注入O2; 从RMG沟槽的侧表面，从底表面的a-Si层和仅仅nFET RMG沟槽的TiN层的剩余部分去除a-Si层和TiN层; 在RMG沟槽中形成Ti层; 在Ti层中垂直注入Al或C并进行退火; 并用Al或W填充RMG沟槽。

公开(公告)号：US08722485B1

公开(公告)日：2014-05-13

申请号：US13851810

申请日：2013-03-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Wei Hua Tong ,  Yiqun Liu ,  Tae-Hoon Kim ,  Seung Kim ,  Haiting Wang ,  Huang Liu

IPC: H01L21/8238

CPC classification number: H01L29/513 ,  H01L21/28167 ,  H01L21/823857 ,  H01L29/78

Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate having formed thereon a sacrificial silicon oxide layer, an interlayer dielectric layer formed over the sacrificial silicon oxide layer, and a dummy gate structure formed over the sacrificial silicon oxide layer and within the interlayer dielectric layer, removing the dummy gate structure to form an opening within the interlayer dielectric layer, and removing the sacrificial silicon oxide layer within the opening to expose the semiconductor substrate within the opening. The method further includes the steps of thermally forming an oxide layer on the exposed semiconductor substrate within the opening, subjecting the thermally formed oxide layer to a decoupled plasma oxidation treatment, and etching the thermally formed oxide layer using a self-saturated wet etch chemistry. Still further, the method includes depositing a high-k dielectric over the thermally formed oxide layer within the opening.

Abstract translation: 一种制造集成电路的方法包括以下步骤：提供其上形成有牺牲氧化硅层的半导体衬底，形成在牺牲氧化硅层上的层间电介质层，以及在牺牲氧化硅层上形成的虚拟栅极结构， 所述层间介电层，去除所述虚拟栅极结构以在所述层间电介质层内形成开口，以及去除所述开口内的所述牺牲氧化硅层以在所述开口内露出所述半导体衬底。 该方法还包括以下步骤：在开口内的暴露的半导体衬底上热氧化形成氧化物层，对热形成的氧化物层进行去耦等离子体氧化处理，以及使用自饱和的湿蚀刻化学法蚀刻热成型的氧化物层。 此外，该方法包括在开口内的热形成的氧化物层上沉积高k电介质。

公开(公告)号：US20210043766A1

公开(公告)日：2021-02-11

申请号：US16533835

申请日：2019-08-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Baofu Zhu ,  Shesh Mani Pandey ,  Jiehui Shu ,  Sipeng Gu ,  Haiting Wang

IPC: H01L29/78 ,  H01L29/66

Abstract: A laterally diffused metal-oxide semiconductor (LDMOS) device is disclosed. The LDMOS FET includes a gate structure between a source region and a drain region over a p-type semiconductor substrate; and a trench isolation partially under the gate structure and between the gate structure and the drain region. A p-well is under and adjacent the source region; and an n-well is under and adjacent the drain region. A counter doping region abuts and is between the p-well and the n-well, and is directly underneath the gate structure. The counter doping region increases drain-source breakdown voltage compares to conventional approaches.

公开(公告)号：US10832966B2

公开(公告)日：2020-11-10

申请号：US15899986

申请日：2018-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Seo Park ,  Haiting Wang ,  Shimpei Yamaguchi ,  Junsic Hong ,  Yong Mo Yang ,  Scott Beasor

IPC: H01L27/115 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.

公开(公告)号：US10832839B1

公开(公告)日：2020-11-10

申请号：US16570575

申请日：2019-09-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Scott Beasor ,  Haiting Wang ,  Sipeng Gu ,  Jiehui Shu

IPC: H01C7/22 ,  H01C1/012 ,  H01C17/00 ,  H01L23/522 ,  H01L49/02

Abstract: Device structures and fabrication methods for an on-chip resistor. A dielectric layer includes a trench with a bottom and a sidewall arranged to surround the bottom. A metal layer is disposed on the dielectric layer at the sidewall of the trench. The metal layer includes a surface that terminates the metal layer at the bottom of the trench to define a discontinuity that extends along a length of the trench.

公开(公告)号：US10818557B2

公开(公告)日：2020-10-27

申请号：US16026130

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sipeng Gu ,  Akshey Sehgal ,  Xinyuan Dou ,  Sunil K. Singh ,  Ravi P. Srivastava ,  Haiting Wang ,  Scott H. Beasor

IPC: H01L21/8234 ,  H01L29/423 ,  H01L23/48 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/66 ,  H01L29/08

Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.