公开(公告)号：US10361289B1

公开(公告)日：2019-07-23

申请号：US15933032

申请日：2018-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Shahab Siddiqui ,  Haiting Wang ,  Ting-Hsiang Hung ,  Yiheng Xu ,  Beth Baumert ,  Jinping Liu ,  Scott Beasor ,  Yue Zhong ,  Shesh Mani Pandey

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/78

Abstract: A method of thermally oxidizing a Si fin to form an oxide layer over the Si fin and then forming an ALD oxide layer over the oxide layer and resulting device are provided. Embodiments include forming a plurality of Si fins on a Si substrate; forming a dielectric layer over the plurality of Si fins and the Si substrate; recessing the dielectric layer, exposing a top portion of the plurality of Si fins; thermally oxidizing surface of the top portion of the plurality of Si fins, an oxide layer formed; and forming an ALD oxide layer over the oxide layer.

公开(公告)号：US20190088766A1

公开(公告)日：2019-03-21

申请号：US15711410

申请日：2017-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani Pandey ,  Jagar Singh ,  Judson R. Holt

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/06

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial sidewall spacer adjacent a sidewall spacer of a transistor and, with the sacrificial sidewall spacer in position, forming openings in an active layer of an SOI substrate adjacent the sacrificial sidewall spacer so as to thereby expose portions of a buried insulation layer of the SOI substrate. In this example, the method also includes performing an isotropic etching process to form recesses of any shape in the buried insulation layer, wherein the recesses extend laterally under a portion of the active layer, and forming an epi semiconductor material in at least the recesses in the buried insulation layer.

公开(公告)号：US10002797B1

公开(公告)日：2018-06-19

申请号：US15420794

申请日：2017-01-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani Pandey

IPC: H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/78 ,  H01L29/73 ,  H01L29/66

CPC classification number: H01L21/8249 ,  H01L27/0623 ,  H01L29/0657 ,  H01L29/66272 ,  H01L29/66666 ,  H01L29/7317 ,  H01L29/732 ,  H01L29/7827

Abstract: Device structures and fabrication methods for a BiCMOS integrated circuit. A first fin and a second fin are formed on a semiconductor substrate. A gate electrode of a vertical field effect transistor is formed in association with the first fin. An emitter of a bipolar junction transistor is formed with an epitaxial growth process on the second fin, and a first source/drain region of the vertical field-effect transistor is concurrently formed with the epitaxial growth process on the first fin. The gate electrode and the first fin are arranged in a vertical direction between the source/drain region and the semiconductor substrate. The second fin is arranged in the vertical direction between the emitter and the semiconductor substrate.

公开(公告)号：US09960113B2

公开(公告)日：2018-05-01

申请号：US15625035

申请日：2017-06-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar Singh ,  Shesh Mani Pandey

IPC: H01L23/522 ,  H01L23/532 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/02186 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31051 ,  H01L23/53228 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/55

Abstract: A method can include applying a patterned mask over a semiconductor structure, the semiconductor structure having a dielectric layer, forming using the patterned mask a material formation trench intermediate first and second spaced apart metal formations formed in the dielectric layer, and disposing a dielectric material formation in the material formation trench.

公开(公告)号：US20180108732A1

公开(公告)日：2018-04-19

申请号：US15292808

申请日：2016-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Baofu Zhu ,  Haifeng Sheng ,  Jinping Liu ,  Shesh Mani Pandey ,  Jagar Singh

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L29/0661 ,  H01L21/3083 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/7851

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to notched fin structures and methods of manufacture. The structure includes: a fin structure composed of a substrate material and a stack of multiple epitaxially grown materials on the substrate material; a notch formed in a first epitaxially grown material of the stack of multiple epitaxially grown materials of the fin structure; an insulator material within the notch of the fin structure; and an insulator layer surrounding the fin structure and above a surface of the notch.

公开(公告)号：US09647145B1

公开(公告)日：2017-05-09

申请号：US15012563

申请日：2016-02-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jagar Singh ,  Shesh Mani Pandey ,  Josef Watts

IPC: H01L29/861 ,  H01L29/06 ,  H01L29/66 ,  H01L27/08

CPC classification number: H01L27/0814 ,  H01L27/0629 ,  H01L29/0657 ,  H01L29/66128 ,  H01L29/66136 ,  H01L29/861 ,  H01L29/8611

Abstract: Diodes for use in FinFET technologies having increased junction electric fields without the need for increased dopant concentrations, as well as methods, apparatus, and systems for fabricating such diodes. The diodes may comprise a semiconductor substrate and a plurality of fins formed on the semiconductor substrate; wherein each of the plurality of fins comprises an N channel doped region comprising an N channel dopant, and the semiconductor substrate further comprises a plurality of P channel doped regions comprising a P channel dopant, wherein each of the P channel doped regions is disposed under one of the plurality of fins and is adjacent to the N channel doped region of the fin.

公开(公告)号：US09577040B2

公开(公告)日：2017-02-21

申请号：US15189079

申请日：2016-06-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie Feng ,  Jianwei Peng ,  Yanxiang Liu ,  Shesh Mani Pandey ,  Francis Benistant

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/268 ,  H01L29/10 ,  H01L29/161 ,  H01L29/167 ,  H01L29/417 ,  H01L21/324 ,  H01L29/165

CPC classification number: H01L29/0847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/105 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions.

Abstract translation: 公开了一种形成具有突然，垂直和共形结的源极/漏极区域的方法以及所得到的器件。 实施例包括在半导体鳍片上方并垂直于半导体鳍片形成栅电极; 在栅电极的相对侧上形成第一间隔物; 在所述翅片的相对侧上形成第二间隔物; 在第二间隔件之间形成邻近第一间隔件的翅片中的空腔; 在每个腔中部分地外延生长源/漏区; 将第一掺杂剂注入部分生长的源极/漏极区域中，其后可选择的RTA; 在空腔中外延生长源/漏区的剩余部分，原位掺杂有第二掺杂剂; 以及在源极/漏极区域中注入第三掺杂剂。

公开(公告)号：US09543297B1

公开(公告)日：2017-01-10

申请号：US14869397

申请日：2015-09-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Konstantin G. Korablev ,  Shesh Mani Pandey ,  Manfred Eller

IPC: H01L21/82 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/10 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L29/1083 ,  H01L29/66795

Abstract: A method of forming fins and the resulting fin-shaped field effect transistors (finFET) are provided. Embodiments include forming silicon (Si) fins over a substrate; forming a first metal over each of the Si fins; forming an isolation material over the first metal; removing an upper portion of the isolation material to expose and upper portion of the first metal; removing the upper portion of the first metal to expose an upper portion of each Si fin; removing the isolation material after removing the upper portion of the first metal; and forming a second metal over the first metal and the upper portion of the Si fins.

Abstract translation: 提供了一种形成翅片的方法和所得的鳍状场效应晶体管（finFET）。 实施例包括在衬底上形成硅（Si）鳍; 在每个Si散热片上形成第一金属; 在所述第一金属上形成隔离材料; 去除所述隔离材料的上部以暴露所述第一金属的上部; 去除第一金属的上部以暴露每个Si散热片的上部; 在去除第一金属的上部之后去除隔离材料; 以及在所述第一金属和所述Si翅片的上部上形成第二金属。

公开(公告)号：US08946039B2

公开(公告)日：2015-02-03

申请号：US13767930

申请日：2013-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Shesh Mani Pandey ,  Roderick Miller ,  Nam Sung Kim

IPC: H01L21/8222 ,  H01L49/02

CPC classification number: H01L28/20

Abstract: Aspects of the present invention relate to an approach for implanting and forming a polysilicon resistor with a single implant dose. Specifically, a mask having a set of openings is formed over a resistor surface. The set of openings are typically formed in a column-row arrangement according to a predetermined pattern. Forming the mask in this manner allows the resistor surface to have multiple regions/zones. A first region is defined by the set of openings in the mask, and a second region is defined by the remaining portions of the mask. The resistor is then subjected to a single implant dose via the openings. Implanting the resistor in this manner allows the resistor to have multiple resistance values (i.e., a first resistance value in the first region, and a second resistance value in the second region).

Abstract translation: 本发明的各方面涉及用单一注入剂量植入和形成多晶硅电阻器的方法。 具体地，在电阻表面上形成具有一组开口的掩模。 一组开口通常根据预定图案以列排布置形成。 以这种方式形成掩模允许电阻器表面具有多个区域/区域。 第一区域由掩模中的一组开口限定，第二区域由掩模的其余部分限定。 然后通过开口对电阻器进行单次注入剂量。 以这种方式植入电阻器，电阻器具有多个电阻值（即，第一区域中的第一电阻值，以及第二区域中的第二电阻值）。