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224 条记录 (耗时 0.029 秒)

    Structure for improving die saw quality
    51.
    发明授权
    Structure for improving die saw quality 有权
    提高模锯质量的结构

    公开(公告)号：US08278737B2

    公开(公告)日：2012-10-02

    申请号：US12417394

    申请日：2009-04-02

    申请人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Ying-Ju Chen ,  Yu-Wen Liu ,  Shin-Puu Jeng

    发明人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Ying-Ju Chen ,  Yu-Wen Liu ,  Shin-Puu Jeng

    IPC分类号： H01L21/00

    CPC分类号： H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device is provided that includes a semiconductor substrate, a plurality of dies formed on the semiconductor substrate, the plurality of dies being separated from one another by a first region extending along a first direction and a second region extending along a second direction different from the first direction, a dummy metal structure formed within a third region that includes a region defined by an intersection of the first region and the second region, a plurality of metal interconnection layers formed over the substrate, and a plurality of dielectric layers formed over the substrate. Each of the metal interconnection layers is disposed within each of the dielectric layers and a dielectric constant of at least one of the dielectric layers is less than about 2.6.

    摘要翻译： 提供了一种半导体器件，其包括半导体衬底，形成在半导体衬底上的多个管芯，所述多个管芯沿着第一方向延伸的第一区域彼此分离，并且沿着不同于第二方向的第二方向延伸的第二区域 第一方向，形成在第三区域内的虚设金属结构，所述第三区域包括由所述第一区域和所述第二区域的交点限定的区域，形成在所述基板上的多个金属互连层，以及形成在所述第二区域上的多个电介质层 基质。 每个金属互连层设置在每个介电层内，并且至少一个电介质层的介电常数小于约2.6。

    Structure to reduce etching residue
    53.
    发明授权
    Structure to reduce etching residue 有权
    结构减少蚀刻残留

    公开(公告)号：US08217499B2

    公开(公告)日：2012-07-10

    申请号：US12952485

    申请日：2010-11-23

    申请人： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Chung-Ying Yang

    发明人： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Chung-Ying Yang

    IPC分类号： H01L23/544

    CPC分类号： H01L21/31144 ,  H01L21/32139 ,  H01L23/585 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure for reducing partially etched materials is described. The structure includes a layout of an intersection area between two trenches. First, a large intersection area having a trapezoidal corner may be replaced with an orthogonal intersection between two trenches. The layout reduces the intersection area as well as the possibility of having partially etched materials left at the intersection area. The structure also includes an alternative way to fill the intersection area with either an un-etched small trapezoidal area or multiple un-etched square areas, so that the opening area at the intersection point is reduced and the possibility of having partially etched materials is reduced too.

    摘要翻译： 描述了用于减少部分蚀刻的材料的结构。 该结构包括两个沟槽之间的交叉区域的布局。 首先，具有梯形角的大交叉区域可以用两个沟槽之间的正交交替来代替。 布局减少了交叉区域以及在交叉区域留下部分蚀刻的材料的可能性。 该结构还包括用未蚀刻的小梯形区域或多个未蚀刻的正方形区域填充交叉区域的替代方法，使得交点处的开口面积减小，并且部分蚀刻材料的可能性降低 太。

    Process for improving the reliability of interconnect structures and resulting structure
    54.
    发明授权
    Process for improving the reliability of interconnect structures and resulting structure 有权
    提高互连结构和结构结构可靠性的方法

    公开(公告)号：US08212330B2

    公开(公告)日：2012-07-03

    申请号：US12879770

    申请日：2010-09-10

    申请人： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

    发明人： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

    IPC分类号： H01L23/52

    CPC分类号： H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L2221/1047

    摘要： An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.

    摘要翻译： 提供了具有改善的可靠性的集成电路的互连结构及其形成方法。 该方法包括提供衬底，形成覆盖在衬底上的电介质层，执行第一收缩过程，其中电介质层收缩并具有第一收缩率，在执行第一收缩过程的步骤之后在介电层中形成导电特征 并且在形成导电特征的步骤之后执行第二收缩过程，其中介电层基本上收缩并且具有第二收缩率。

    PAD STRUCTURE AND METHOD OF TESTING
    57.
    发明申请
    PAD STRUCTURE AND METHOD OF TESTING 有权
    PAD结构和测试方法

    公开(公告)号：US20100123135A1

    公开(公告)日：2010-05-20

    申请号：US12693501

    申请日：2010-01-26

    申请人： Hsien-Wei Chen

    发明人： Hsien-Wei Chen

    IPC分类号： H01L23/58 ,  H01L21/66

    CPC分类号： H01L22/32 ,  H01L22/34 ,  H01L2224/02166

    摘要： An interconnect structure includes: a plurality of dielectric layers having aligned process control monitor (PCM) pads, and a conductive structure above a topmost one of the PCM pads. The conductive structure electrically connects the topmost PCM pad to a device under test above a level of the topmost PCM pad. The conductive structure is sized and shaped so as to leave a majority portion of the topmost PCM pad exposed for access by a test probe.

    摘要翻译： 互连结构包括：具有对准的过程控制监视器（PCM）焊盘的多个电介质层，以及位于最上面的PCM焊盘之上的导电结构。 导电结构将最上面的PCM焊盘电连接到被测器件的最高PCM焊盘的电平之上。 导电结构的尺寸和形状使得留下最高PCM垫的大部分暴露以供测试探针进入。

    SEMICONDUCTOR TEST PAD STRUCTURES
    58.
    发明申请
    SEMICONDUCTOR TEST PAD STRUCTURES 有权

    公开(公告)号：US20100117080A1

    公开(公告)日：2010-05-13

    申请号：US12267021

    申请日：2008-11-07

    申请人： Hsien-Wei Chen ,  Ying-Ju Chen ,  Yu-Wen Liu ,  Hao-Yi Tsai ,  Shin-Puu Jeng

    发明人： Hsien-Wei Chen ,  Ying-Ju Chen ,  Yu-Wen Liu ,  Hao-Yi Tsai ,  Shin-Puu Jeng

    IPC分类号： H01L23/485

    CPC分类号： H01L22/34 ,  H01L24/05 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

    摘要： A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.

    摘要翻译： 具有集成的模具隔离保护屏障的半导体测试焊盘互连结构。 互连结构包括多个堆叠的金属层，每个层具有通过介电材料层与其它测试焊盘分离的导电测试焊盘。 在一个实施例中，至少一个金属通孔条被嵌入到互连结构中，并将金属层中的每个测试焊盘电连接在一起。 在一些实施例中，通孔棒基本上沿着由每个测试垫限定的整个第一侧面延伸。 在其他实施例中，可以提供一对相对的通孔条，其布置在限定在半导体晶片上的划线带中的模切单切锯切线的相对侧上。

    Backend Interconnect Scheme with Middle Dielectric Layer Having Improved Strength
    59.
    发明申请
    Backend Interconnect Scheme with Middle Dielectric Layer Having Improved Strength 有权
    后置互连方案与中间介质层具有改进的强度

    公开(公告)号：US20090283911A1

    公开(公告)日：2009-11-19

    申请号：US12121541

    申请日：2008-05-15

    申请人： Hao-Yi Tsai ,  Yu-Wen Liu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shin-Puu Jeng

    发明人： Hao-Yi Tsai ,  Yu-Wen Liu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shin-Puu Jeng

    IPC分类号： H01L23/522

    CPC分类号： H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05556 ,  H01L2924/14 ,  H01L2924/00

    摘要： An integrated circuit structure includes a first, a second and a third metallization layer. The first metallization layer includes a first dielectric layer having a first k value; and first metal lines in the first dielectric layer. The second metallization layer is over the first metallization layer, and includes a second dielectric layer having a second k value greater than the first k value; and second metal lines in the second dielectric layer. The third metallization layer is over the second metallization layer, and includes a third dielectric layer having a third k value; and third metal lines in the third dielectric layer. The integrated circuit structure further includes a bottom passivation layer over the third metallization layer.

    摘要翻译： 集成电路结构包括第一，第二和第三金属化层。 第一金属化层包括具有第一k值的第一介电层; 和第一介电层中的第一金属线。 第二金属化层在第一金属化层之上，并且包括具有大于第一k值的第二k值的第二介电层; 和第二介电层中的第二金属线。 第三金属化层在第二金属化层之上，并且包括具有第三k值的第三介电层; 和第三介电层中的第三金属线。 集成电路结构还包括在第三金属化层上的底部钝化层。