公开(公告)号：US20240319591A1

公开(公告)日：2024-09-26

申请号：US18189189

申请日：2023-03-23

Applicant: International Business Machines Corporation

Inventor： Steven Holmes ,  Pouya Hashemi ,  Robert L. Bruce ,  Eric A. Joseph ,  Yanning Sun

IPC: G03F7/00 ,  H01J37/305

CPC classification number: G03F7/0015 ,  G03F7/0002 ,  H01J37/3053 ,  H01F41/22

Abstract: A semiconductor structure includes a first plurality of slanted features within a first region of a substrate. Two or more magnetic guiding structures are embedded within the first region of the substrate. The first plurality of slanted features is located between the two or more magnetic guiding structures for varying a magnetic field strength around the first plurality of slanted features. A second plurality of slanted features are located within a second region of the substrate. The second region of the substrate is adjacent to the first region of the substrate. The second plurality of slanted features include a second orientation angle that is different from a first orientation angle of the first plurality of slanted features.

公开(公告)号：US09911648B2

公开(公告)日：2018-03-06

申请号：US15347969

申请日：2016-11-10

Applicant: International Business Machines Corporation

Inventor： Brett C. Baker-O'Neal ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/532 ,  H01L21/027 ,  H01L21/033 ,  H01L23/528

CPC classification number: H01L21/76892 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32131 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/528 ,  H01L23/53242 ,  H01L23/53247 ,  H01L23/53252 ,  H01L23/53295

Abstract: A method for forming at least one Ag or Ag based alloy feature in an integrated circuit, including providing a blanket layer of Ag or Ag based alloy in a multi-layer structure on a substrate. The method further includes providing a hard mask layer over the blanket layer of Ag or Ag based alloy. The method further includes performing an etch of the blanket layer of Ag or Ag based alloy, wherein a portion of the blanket layer of Ag or Ag based alloy that remains after the etch forms one or more conductive lines. The method further includes forming a liner that surrounds the one or more conductive lines. The method further includes depositing a dielectric layer on the multi-layer structure.

公开(公告)号：US09799552B2

公开(公告)日：2017-10-24

申请号：US14949386

申请日：2015-11-23

Applicant: International Business Machines Corporation

Inventor： Stephen M. Gates ,  Gregory M. Fritz ,  Eric A. Joseph ,  Terry A. Spooner

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76814 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76888 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53266

Abstract: A semiconductor device and a method of fabricating a contact to interface with an interconnect in a semiconductor device are described. The device includes a dielectric layer formed on a semiconductor layer, and a contact fabricated in a via formed within the dielectric layer. An interconnect formed above the contact interfaces with an exposed surface of the contact opposite a surface closest to the semiconductor layer. The contact includes a contact material in a first portion of the contact and an interface metal in a second portion of the contact.

公开(公告)号：US09786597B2

公开(公告)日：2017-10-10

申请号：US13793859

申请日：2013-03-11

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/48 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Self-aligned pitch split techniques for metal wiring involving a hybrid (subtractive patterning/damascene) metallization approach are provided. In one aspect, a method for forming a metal wiring layer on a wafer includes the following steps. A copper layer is formed on the wafer. A patterned hardmask is formed on the copper layer. The copper layer is subtractively patterned using the patterned hardmask to form a plurality of first copper lines. Spacers are formed on opposite sides of the first copper lines. A planarizing dielectric material is deposited onto the wafer, filling spaces between the first copper lines. One or more trenches are etched in the planarizing dielectric material. The trenches are filled with copper to form a plurality of second copper lines that are self-aligned with the first copper lines. An electronic device is also provided.

公开(公告)号：US09711365B2

公开(公告)日：2017-07-18

申请号：US14268098

申请日：2014-05-02

Applicant: International Business Machines Corporation ,  ZEON Corporation

Inventor： Eric A. Joseph ,  Goh Matsuura ,  Masahiro Nakamura ,  Edmund M. Sikorski ,  Bang N. To

IPC: H01L21/302 ,  H01L21/461 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/768

CPC classification number: H01L21/3065 ,  H01L21/30655 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/768 ,  H01L21/76898

Abstract: Pretreatment of an etch chamber for performing a silicon etch process and Bosch process can be effected by running a deposition process employing C5HF7, or by running an alternating deposition and etch process employing C5H2F6 and SF6. It has been discovered that the pretreatment of the etch chamber for the silicon etch process can enhance the etch rate of silicon by at least 50% without adverse effect on etch profile during a first each process following the pretreatment, while the etch rate enhancement factor decreases over time. By periodically performing the pretreatment in the etch chamber, the throughput of the etch chamber can be increased without adversely impacting the etch profile of the processed substrates.

公开(公告)号：US09691972B1

公开(公告)日：2017-06-27

申请号：US14976339

申请日：2015-12-21

Applicant: International Business Machines Corporation ,  Tokyo Electron Limited

Inventor： Anthony J. Annunziata ,  Sebastian U. Engelmann ,  Eric A. Joseph ,  Gen P. Lauer ,  Nathan P. Marchack ,  Deborah A. Neumayer ,  Masahiro Yamazaki

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: A method of making a magnetic random access memory device comprises forming a magnetic tunnel junction on an electrode, the magnetic tunnel junction comprising a reference layer positioned in contact with the electrode, a tunnel barrier layer arranged on the reference layer, and a free layer arranged on the tunnel barrier layer; and depositing an encapsulating layer on and along sidewalls of the magnetic tunnel junction at a temperature of 40 to 60° C. using remote microwave plasma deposition wherein the encapsulation layer comprises silicon and nitrogen. An MRAM device made by the aforementioned method is also disclosed.

公开(公告)号：US20170179023A1

公开(公告)日：2017-06-22

申请号：US15430667

申请日：2017-02-13

Applicant: International Business Machines Corporation

Inventor： Robert L. Bruce ,  Gregory M. Fritz ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/285 ,  H01L23/522 ,  H01L23/532 ,  H01L21/3213 ,  H01L21/288

CPC classification number: H01L23/528 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53252 ,  H01L24/05 ,  H01L2224/05025 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147

Abstract: In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.

公开(公告)号：US20170062274A1

公开(公告)日：2017-03-02

申请号：US15347969

申请日：2016-11-10

Applicant: International Business Machines Corporation

Inventor： Brett C. Baker-O'Neal ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/532 ,  H01L21/027 ,  H01L21/3213 ,  H01L23/528

CPC classification number: H01L21/76892 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32131 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/528 ,  H01L23/53242 ,  H01L23/53247 ,  H01L23/53252 ,  H01L23/53295

Abstract: A method for forming at least one Ag or Ag based alloy feature in an integrated circuit, including providing a blanket layer of Ag or Ag based alloy in a multi-layer structure on a substrate. The method further includes providing a hard mask layer over the blanket layer of Ag or Ag based alloy. The method further includes performing an etch of the blanket layer of Ag or Ag based alloy, wherein a portion of the blanket layer of Ag or Ag based alloy that remains after the etch forms one or more conductive lines. The method further includes forming a liner that surrounds the one or more conductive lines. The method further includes depositing a dielectric layer on the multi-layer structure.

Abstract translation: 一种用于在集成电路中形成至少一种Ag或Ag基合金特征的方法，包括在基底上以多层结构提供Ag或Ag基合金的覆盖层。 该方法还包括在Ag或Ag基合金的覆盖层上提供硬掩模层。 该方法还包括对Ag或Ag基合金的覆盖层进行蚀刻，其中在蚀刻后保留的Ag或Ag基合金的覆盖层的一部分形成一个或多个导电线。 所述方法还包括形成围绕所述一条或多条导电线的衬里。 该方法还包括在多层结构上沉积介电层。

公开(公告)号：US20170040258A1

公开(公告)日：2017-02-09

申请号：US15157906

申请日：2016-05-18

Applicant: International Business Machines Corporation

Inventor： Robert L. Bruce ,  Gregory M. Fritz ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/528 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53252 ,  H01L24/05 ,  H01L2224/05025 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147

Abstract: In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.

公开(公告)号：US09564362B2

公开(公告)日：2017-02-07

申请号：US14615077

申请日：2015-02-05

Applicant: International Business Machines Corporation

Inventor： Brett C. Baker-O'Neal ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/532

CPC classification number: H01L21/76892 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32131 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/528 ,  H01L23/53242 ,  H01L23/53247 ,  H01L23/53252 ,  H01L23/53295

Abstract: A method for forming at least one Ag or Ag based alloy feature in an integrated circuit, including providing a blanket layer of Ag or Ag based alloy in a multi-layer structure on a substrate. The method further includes providing a hard mask layer over the blanket layer of Ag or Ag based alloy. The method further includes performing an etch of the blanket layer of Ag or Ag based alloy, wherein a portion of the blanket layer of Ag or Ag based alloy that remains after the etch forms one or more conductive lines. The method further includes forming a liner that surrounds the one or more conductive lines. The method further includes depositing a dielectric layer on the multi-layer structure.

Abstract translation: 一种用于在集成电路中形成至少一种Ag或Ag基合金特征的方法，包括在基底上以多层结构提供Ag或Ag基合金的覆盖层。 该方法还包括在Ag或Ag基合金的覆盖层上提供硬掩模层。 该方法还包括对Ag或Ag基合金的覆盖层进行蚀刻，其中在蚀刻后保留的Ag或Ag基合金的覆盖层的一部分形成一个或多个导电线。 所述方法还包括形成围绕所述一条或多条导电线的衬里。 该方法还包括在多层结构上沉积介电层。