公开(公告)号：US20200091608A1

公开(公告)日：2020-03-19

申请号：US16472830

申请日：2017-12-20

Applicant: Intel Corporation

Inventor： Erkan Alpman ,  Arnaud Lucres Amadjikpe ,  Omer Asaf ,  Kameran Azadet ,  Rotem Banin ,  Miroslav Baryakh ,  Anat Bazov ,  Stefano Brenna ,  Bryan K. Casper ,  Anandaroop Chakrabarti ,  Gregory Chance ,  Debabani Choudhury ,  Emanuel Cohen ,  Claudio Da Silva ,  Sidharth Dalmia ,  Saeid Daneshgar Asl ,  Kaushik Dasgupta ,  Kunal Datta ,  Brandon Davis ,  Ofir Degani ,  Amr M. Fahim ,  Amit Freiman ,  Michael Genossar ,  Eran Gerson ,  Eyal Goldberger ,  Eshel Gordon ,  Meir Gordon ,  Josef Hagn ,  Shinwon Kang ,  Te Yu Kao ,  Noam Kogan ,  Mikko S. Komulainen ,  Igal Yehuda Kushnir ,  Saku Lahti ,  Mikko M. Lampinen ,  Naftali Landsberg ,  Wook Bong Lee ,  Run Levinger ,  Albert Molina ,  Resti Montoya Moreno ,  Tawfiq Musah ,  Nathan G. Narevsky ,  Hosein Nikopour ,  Oner Orhan ,  Georgios Palaskas ,  Stefano Pellerano ,  Ron Pongratz ,  Ashoke Ravi ,  Shmuel Ravid ,  Peter Andrew Sagazio ,  Eren Sasoglu ,  Lior Shakedd ,  Gadi Shor ,  Baljit Singh ,  Menashe Soffer ,  Ra'anan Sover ,  Shilpa Talwar ,  Nebil Tanzi ,  Moshe Teplitsky ,  Chintan S. Thakkar ,  Jayprakash Thakur ,  Avi Tsarfati ,  Yossi Tsfati ,  Marian Verhelst ,  Nir Weisman ,  Shuhei Yamada ,  Ana M. Yepes ,  Duncan Kitchin

IPC: H01Q9/04 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q1/24 ,  H01Q5/47 ,  H01Q3/24 ,  H01Q21/24 ,  H04B1/3827 ,  H04B15/04 ,  H04B7/0456 ,  H04B7/06 ,  H03L7/14

Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

公开(公告)号：US10164800B2

公开(公告)日：2018-12-25

申请号：US15475783

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Albert Molina ,  Kameran Azadet

IPC: H04L25/02 ,  H04L27/26 ,  H04B7/0413 ,  H04J13/00

Abstract: An apparatus and a method for estimation a wireless channel are disclosed. For example, the method correlates, by a correlator, a plurality of signals of a combined signal received by a receive antenna over the wireless channel from a plurality of transmit antennas, with respective DMRSs of the plurality of transmit antennas, converts, by a converter, the correlated plurality of signals from frequency to time domain, iteratively peak cancels, by a peak canceller, a largest peak of the combined impulse response and stores a scaling factor and location pair of the cancelled peak until a magnitude of a next largest peak is below a predetermined threshold, assigns, by an assigner, each of the scaling factor and location pairs to a transmit antenna, and estimates, by an estimator, for each of the plurality of transmit antennas, the wireless channel based on the assigned scaling factor and location pairs.

公开(公告)号：US09960900B2

公开(公告)日：2018-05-01

申请号：US14230607

申请日：2014-03-31

Applicant: Intel Corporation

Inventor： Kameran Azadet

IPC: H04K1/02 ,  H04L25/03 ,  H04L25/49 ,  H04L5/14 ,  H04L25/08 ,  G06F17/50 ,  H04B1/62 ,  H04L1/00 ,  H04B1/04 ,  G06F17/15 ,  G06F9/30 ,  H04L27/36 ,  H04J11/00 ,  H04B1/525

CPC classification number: H04L5/1461 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/50 ,  G06F17/5009 ,  H04B1/0475 ,  H04B1/525 ,  H04B1/62 ,  H04B2001/0425 ,  H04J11/004 ,  H04L1/0043 ,  H04L25/03012 ,  H04L25/03343 ,  H04L25/08 ,  H04L27/367 ,  H04L27/368

Abstract: Methods and apparatus are provided for modeling of a physical system using two-dimensional look-up tables. A method can include determining coefficients for a piece-wise polynomial function that estimates a non-linear function, storing the coefficients as entries in one or more two-dimensional look up tables in the memory, receiving a complex value input corresponding to an actual input value, identifying two closest entries, a first closest entry and a second closest entry, to the complex input value in a two-dimensional look-up table of the one or more two-dimensional look-up tables, evaluating, using the one or more hardware processors, the piece-wise polynomial function at the complex input value twice, a first evaluation using the coefficients corresponding to the first closest entry and a second evaluation using the coefficients corresponding to the second closest entry, to generate first and second output values, and generating an output value by performing a linear interpolation between the first and second output values.

公开(公告)号：US09602127B1

公开(公告)日：2017-03-21

申请号：US15041326

申请日：2016-02-11

Applicant: Intel Corporation

Inventor： Kameran Azadet

IPC: H03M7/34 ,  H03M7/38 ,  H03M7/30 ,  H04L29/06

CPC classification number: H03M7/3082 ,  H03M5/02 ,  H03M7/3066

Abstract: Devices and methods of reducing quantization noise using a pyramid stream encoder are generally described. Groups of D digital symbols are iteratively computed for a digital signal such that each group of symbols minimizes a norm of a weighted residue vector. The weighted residue vector is formed by applying predetermined weighting coefficients to components of a residue vector. Each component is a difference between a sample of the digital signal and a linear combination of different groups of digital symbols with predefined filter coefficients. The norm of the weighted residue vector evaluated at a rate D times slower than a sampling rate of an output signal. The groups of D digital symbols are provided as the output signal.

公开(公告)号：US12261637B2

公开(公告)日：2025-03-25

申请号：US17358040

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Marc Jan Georges Tiebout

IPC: H04B1/04 ,  H04L5/12 ,  H04L25/06

Abstract: A method and apparatus for cancelling local oscillator feedthrough (LOFT). A transmitter includes a first mixer configured to mix a transmit signal with a first local oscillator signal. An observation receiver receives a fraction of a power of the transmit signal as a feedback signal and processes the feedback signal. The observation receiver includes a second mixer configured to mix the feedback signal with a second local oscillator signal. A LOFT correction estimation circuitry is configured to determine a DC offset to cancel LOFT at the first mixer in the transmitter based on measurements on outputs of the second mixer. An LOFT correction circuitry is configured to add the DC offset to the transmit signal. The LOFT correction estimation circuitry may determine the DC offset based on several measurements obtained by varying the DC offset and a phase shift in the second local oscillator signal in the observation receiver.

公开(公告)号：US12237589B2

公开(公告)日：2025-02-25

申请号：US17734529

申请日：2022-05-02

Applicant: Intel Corporation

Inventor： Erkan Alpman ,  Arnaud Lucres Amadjikpe ,  Omer Asaf ,  Kameran Azadet ,  Rotem Banin ,  Miroslav Baryakh ,  Anat Bazov ,  Stefano Brenna ,  Bryan K. Casper ,  Anandaroop Chakrabarti ,  Gregory Chance ,  Debabani Choudhury ,  Emanuel Cohen ,  Claudio Da Silva ,  Sidharth Dalmia ,  Saeid Daneshgar Asl ,  Kaushik Dasgupta ,  Kunal Datta ,  Brandon Davis ,  Ofir Degani ,  Amr M. Fahim ,  Amit Freiman ,  Michael Genossar ,  Eran Gerson ,  Eyal Goldberger ,  Eshel Gordon ,  Meir Gordon ,  Josef Hagn ,  Shinwon Kang ,  Te Yu Kao ,  Noam Kogan ,  Mikko S. Komulainen ,  Igal Yehuda Kushnir ,  Saku Lahti ,  Mikko M. Lampinen ,  Naftali Landsberg ,  Wook Bong Lee ,  Run Levinger ,  Albert Molina ,  Resti Montoya Moreno ,  Tawfiq Musah ,  Nathan G. Narevsky ,  Hosein Nikopour ,  Oner Orhan ,  Georgios Palaskas ,  Stefano Pellerano ,  Ron Pongratz ,  Ashoke Ravi ,  Shmuel Ravid ,  Peter Andrew Sagazio ,  Eren Sasoglu ,  Lior Shakedd ,  Gadi Shor ,  Baljit Singh ,  Menashe Soffer ,  Ra'anan Sover ,  Shilpa Talwar ,  Nebil Tanzi ,  Moshe Teplitsky ,  Chintan S. Thakkar ,  Jayprakash Thakur ,  Avi Tsarfati ,  Yossi Tsfati ,  Marian Verhelst ,  Nir Weisman ,  Shuhei Yamada ,  Ana M. Yepes ,  Duncan Kitchin

IPC: H01Q5/47 ,  H01Q1/24 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q3/24 ,  H01Q9/04 ,  H01Q21/24 ,  H03L7/14 ,  H04B1/3827 ,  H04B7/0456 ,  H04B7/06 ,  H04B15/04

Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

公开(公告)号：US12034450B2

公开(公告)日：2024-07-09

申请号：US17754308

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Daniel Gruber ,  Ramon Sanchez ,  Kameran Azadet ,  Martin Clara

IPC: H03M1/10 ,  H03M1/06

CPC classification number: H03M1/1033 ,  H03M1/0626

Abstract: An apparatus for correcting a mismatch between a first segment and a second segment of a Digital-to-Analog Converter, DAC, is provided. The first segment generates a first contribution to an analog output signal of the DAC based on a first number of bits of a digital input word for the DAC converter, and the second segment generates a second contribution based on a second number of bits. Further, the apparatus comprises a first processing circuit for the first number of bits comprising a first filter configured to modify the first number of bits to generate first modified bits, and a second processing circuit comprising a second filter to modify the second number of bits to generate second modified bits. The apparatus additionally comprises an output configured to output a modified digital input word for the DAC, which is based on the first modified bits and the second modified bits.

公开(公告)号：US12028090B2

公开(公告)日：2024-07-02

申请号：US17754310

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Albert Molina ,  Kameran Azadet ,  Martin Clara ,  Hundo Shin

IPC: H03M1/66 ,  H03M1/80

CPC classification number: H03M1/808

Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals. Further, the digital-to-analog converter includes a plurality of groups of inverter cells. Each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals. The inverter cells includes a respective inverter circuit configured to invert the respective delayed digital input signal. The plurality of groups of inverter cells include different numbers of inverter cells. The digital-to-analog converter additionally includes an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.

公开(公告)号：US11901908B2

公开(公告)日：2024-02-13

申请号：US17754148

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Daniel Gruber ,  Kameran Azadet ,  Yu-Shan Wang ,  Hundo Shin ,  Martin Clara

IPC: H04B1/04 ,  H03M1/06 ,  H04B1/10

CPC classification number: H03M1/0614 ,  H04B1/0475 ,  H04B1/1018

Abstract: A Digital-to-Analog Converter, DAC, is provided. The DAC comprises one or more first DAC cells configured to generate a first analog signal based on first digital data. The one or more first DAC cells are coupled to a first output node for coupling to a first load. The DAC comprises one or more second DAC cells configured to generate a second analog signal based on second digital data. The one or more second DAC cells are coupled to a second output node for coupling to a second load. The one or more first DAC cells and the one or more second DAC cells are couplable to a power supply for drawing a supply current. The DAC further comprises a data generation circuit configured to generate the second digital data based on the first digital data.

公开(公告)号：US20240008045A1

公开(公告)日：2024-01-04

申请号：US17853194

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Kannan Rajamani ,  Kameran Azadet ,  Kevin Kinney ,  Thomas Smith ,  Zoran Zivkovic

IPC: H04W72/04 ,  H04J3/06

CPC classification number: H04W72/042 ,  H04J3/0661

Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted and a measured or observed transmission of the data samples. By comparing these blocks of data samples, DFE functions such as digital pre-distortion (DPD) parameter adaptation may be implemented. The hybrid architecture enables high flexibility at low additional cost. To further limit the costs, the programable processing array may have processing power and memory that is reduced compared to conventional processing array implementations.