中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

135 records (took 0.021 seconds)

    Stubby pads for channel cross-talk reduction
    51.
    发明授权
    Stubby pads for channel cross-talk reduction 有权
    短路焊盘，用于通道串扰降低

    公开(公告)号：US09105635B2

    公开(公告)日：2015-08-11

    申请号：US13801998

    申请日：2013-03-13

    Applicant: INTEL CORPORATION

    Inventor： Nevin Altunyurt ,  Tolga Memioglu ,  Kemal Aygun

    IPC: H01L23/498 ,  H01L23/522 ,  H01L23/66

    CPC classification number: H01L23/5226 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/642 ,  H01L23/66 ,  H01L2223/6633 ,  H01L2224/16237 ,  H01L2224/16265 ,  H01L2224/16267 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A metal surface feature, such as a pad, terminating a vertical transition through a substrate, such as an IC package substrate, includes one or more stubs providing high edge surface area to couple with one or more complementary stubs on an adjacent metal surface feature to provide a desired amount of mutual capacitance that may at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent pads is provided for more than two pads to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, the pads have a large pitch (e.g., 1000 μm) suitable for interfacing to an interposer or PCB socket, while the gap between the stubs is small (e.g., 15 μm), as limited only by the minimum spacing allowed for metal features on the opposite side of the package employed for interfacing to the IC.

    Abstract translation: 金属表面特征，例如衬垫，终止垂直过渡通过诸如IC封装衬底的衬底的一个或多个衬底，其提供高边缘表面积以与相邻金属表面特征上的一个或多个互补短截线耦合的短截线 提供期望量的互电容，其可以至少部分地消除整个信道串扰（例如，FEXT）减少的串扰。 在实施例中，为多于两个焊盘提供相邻焊盘的​​电容耦合以实现多于一个受害者 - 侵略者对的串扰减少和/或实现两个以上侵略者的串扰减少。 在实施例中，焊盘具有适于与插入件或PCB插座对接的大间距（例如，1000μm），而短截线之间的间隙较小（例如，15μm），仅受金属允许的最小间隔的限制 用于与IC连接的封装的相对侧的特征。

    Density-graded adhesion layer for conductors
    56.
    发明授权
    Density-graded adhesion layer for conductors 有权

    公开(公告)号：US11508676B2

    公开(公告)日：2022-11-22

    申请号：US16412464

    申请日：2019-05-15

    Applicant: Intel Corporation

    Inventor： Rahul N. Manepalli ,  Kemal Aygun ,  Srinivas V. Pietambaram ,  Cemil S. Geyik

    IPC: H01L23/66 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

    Abstract: Density-graded adhesion layers on conductive structures within a microelectronic package substrate are described. An example is a density-graded adhesion layer that includes a dense region proximate to a conductive structure that is surrounded by a less dense (or porous) region adjacent to an overlying dielectric layer. Providing such a graded adhesion layer can have a number of benefits, which can include providing both mechanical connections for improved adhesion with a surrounding dielectric layer and provide hermetic protection for the underlying conductive structure from corrosive species. The adhesion layer enables the conductive structure to maintain its as-formed smooth surface which in turn reduces insertion loss of signals transmitted through the conductive structure.

    High density interconnect structures configured for manufacturing and performance
    57.
    发明授权
    High density interconnect structures configured for manufacturing and performance 有权

    公开(公告)号：US11387188B2

    公开(公告)日：2022-07-12

    申请号：US17091657

    申请日：2020-11-06

    Applicant: Intel Corporation

    Inventor： Henning Braunisch ,  Kemal Aygun ,  Ajay Jain ,  Zhiguo Qian

    IPC: H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L23/14 ,  H01L23/31

    Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

    Horizontal pitch translation using embedded bridge dies
    59.
    发明授权
    Horizontal pitch translation using embedded bridge dies 有权

    公开(公告)号：US11276635B2

    公开(公告)日：2022-03-15

    申请号：US16636620

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Sujit Sharan ,  Kemal Aygun ,  Zhiguo Qian ,  Yidnekachew Mekonnen ,  Zhichao Zhang ,  Jianyong Xie

    IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00

    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

    Ground via clustering for crosstalk mitigation
    60.
    发明授权
    Ground via clustering for crosstalk mitigation 有权

    公开(公告)号：US11244890B2

    公开(公告)日：2022-02-08

    申请号：US17074820

    申请日：2020-10-20

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

    IPC: H01L23/498 ,  H01L21/48

    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

Patent Agency Ranking