公开(公告)号：US09099394B2

公开(公告)日：2015-08-04

申请号：US14066119

申请日：2013-10-29

申请人： International Business Machines Corporation

发明人： Nicolas Breil ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC分类号： H01L27/112 ,  H01L21/28 ,  H01L29/51 ,  H01L29/788 ,  H01L27/115 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L29/49

CPC分类号： H01L21/28273 ,  H01L21/0228 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/11546 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7881

摘要： A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.

摘要翻译： 在半导体衬底上同时形成用于场效应晶体管（FET）的高介电常数（高k）栅极电介质和非易失性随机存取存储器（NVRAM）器件的高k隧道电介质。 随后沉积至少一个导电材料层，控制栅极电介质层和一次性材料层的堆叠并且被光刻图案化。 沉积并图案化平坦化介电层，并且去除一次性材料部分。 控制栅极电介质层的剩余部分保留在NVRAM器件区域中，但在FET区域中被去除。 导电材料沉积在栅极腔中以为NVRAM器件提供控制栅极和用于FET的栅极部分。 或者，控制栅介质层可以用NVRAM器件区域中的高k控制栅极电介质代替。

公开(公告)号：US20140252503A1

公开(公告)日：2014-09-11

申请号：US13793804

申请日：2013-03-11

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Michael P. Chudzik ,  Barry P. Linder ,  Shahab Siddiqui

IPC分类号： H01L21/02 ,  H01L27/088

CPC分类号： H01L29/513 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/02318 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/2807 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/324 ,  H01L21/823412 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/161 ,  H01L29/42364 ,  H01L29/518

摘要： A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.

摘要翻译： 可以通过利用第一原子层沉积工艺沉积第一氧化硅材料来形成栅极电介质。 选择第一氧化硅材料的厚度以对应于第一原子层沉积工艺的至少10个沉积循环。 通过第一等离子体氮化工艺将第一氧化硅材料转化为第一氮氧化硅材料。 随后通过第二原子层沉积工艺沉积第二氧化硅材料。 通过第二等离子体氮化处理将第二氧化硅材料转化为第二氮氧化硅材料。 原子层沉积工艺和等离子体氮化处理的多次重复提供氮氮原子与氧原子的比例大于1/3的氮氧化硅材料，其可以有利地用于减少通过栅极电介质的漏电流。

公开(公告)号：US20140170844A1

公开(公告)日：2014-06-19

申请号：US14167532

申请日：2014-01-29

申请人： International Business Machines Corporation

发明人： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

IPC分类号： H01L21/28

CPC分类号： H01L21/28008 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

摘要： A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) is provided. Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack may also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein.

摘要翻译： 提供包括缩放的n沟道场效应晶体管（nFET）和缩放的p沟道场效应晶体管（pFET）的互补金属氧化物半导体（CMOS）结构。 通过在nFET栅极堆叠内形成等离子体氮化的nFET阈值电压调整的高k栅极电介质层部分，以及在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分来提供这种结构。 pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也可以等离子体氮化。 等离子体氮化nFET阈值电压调节的高k栅极电介质层部分包括高达15原子％的N 2和位于其中的nFET阈值电压调节的物质。

公开(公告)号：US20140106531A1

公开(公告)日：2014-04-17

申请号：US13677489

申请日：2012-11-15

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Cyril Cabral, Jr. ,  Josephine B. Chang ,  Michael P. Chudzik ,  Martin M. Frank ,  Michael A. Guillorn ,  Christian Lavoie ,  Shreesh Narasimha ,  Vijay Narayanan

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66507 ,  H01L29/6659

摘要： A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy layer present on a work function metal layer, and a dielectric capping layer present on the metal semiconductor alloy layer. The at least one gate sidewall spacer and the dielectric capping layer may encapsulate the metal semiconductor alloy layer within the gate structure.

摘要翻译： 一种半导体器件，包括存在于半导体衬底的沟道部分上的栅极结构和邻近栅极结构的至少一个栅极侧壁间隔物。 在一个实施例中，栅极结构包括存在于栅极电介质层上的功函数金属层，存在于功函数金属层上的金属半导体合金层和存在于金属半导体合金层上的电介质覆盖层。 所述至少一个栅极侧壁间隔物和介电覆盖层可以将栅极结构内的金属半导体合金层封装。

公开(公告)号：US20140070293A1

公开(公告)日：2014-03-13

申请号：US14080291

申请日：2013-11-14

申请人： International Business Machines Corporation

发明人： Zhengwen Li ,  Damon B. Farmer ,  Michael P. Chudzik ,  Chengwen Pei ,  Keith Kwong Hon Wong ,  Jian Yu ,  Zhen Zhang

IPC分类号： H01L27/108

CPC分类号： H01L27/10829 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/945

摘要： A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.

摘要翻译： 提供一种存储器件和形成存储器件的方法，其包括具有金属半导体合金的下电极的电容器。 在一个实施例中，存储器件包括存在于半导体衬底中的沟槽，其包括在掩埋介电层顶部上的绝缘（SOI）半导体层，其中所述掩埋介电层位于基底半导体层的顶部。 电容器存在于沟槽中，其中电容器包括金属半导体合金的下电极，其具有与基底半导体层的上表面自对准的上边缘，高k电介质节点层和上层 金属电极。 存储器件还包括与电容器电连通的传输晶体管。

公开(公告)号：US20130161764A1

公开(公告)日：2013-06-27

申请号：US13770552

申请日：2013-02-19

申请人： International Business Machines Corporation

发明人： Keith Kwong Hon Wong ,  Michael P. Chudzik ,  Unoh Kwon

IPC分类号： H01L29/51

CPC分类号： H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

摘要： Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly.

摘要翻译： 提供了替代栅极堆叠，这增加了p型场效应晶体管（PFET）的栅电极的功函数。 在一个实施例中，功函数金属堆叠包括位于下部氮化钛层和上部氮化钛层之间的氧化钛 - 氮化物层。 下部氮化钛层，钛氧化物 - 氮化物层和上部氮化钛层的堆叠产生显着增加功函数金属叠层功函数的意想不到的结果。 在另一个实施例中，功函数金属堆叠包括在不高于420℃的温度下沉积的铝层。在不高于420℃的温度下沉积的铝层产生增加工件功函数的意想不到的结果 功能金属堆叠显着。

公开(公告)号：US20130143377A1

公开(公告)日：2013-06-06

申请号：US13752567

申请日：2013-01-29

申请人： International Business Machines Corporation

发明人： Shahab Siddiqui ,  Michael P. Chudzik ,  Carl J. Radens

IPC分类号： H01L29/66

CPC分类号： H01L29/66575 ,  H01L21/28088 ,  H01L21/76897 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a substrate. A mandrel dielectric layer is formed overlying source and drain regions of the substrate. The replacement gate structure is removed to provide an opening exposing the channel region of the substrate. A functional gate structure is formed over the channel region including a work function metal layer. A protective cap structure is formed over the functional gate structure. At least one via is etched through the mandrel dielectric layer selective to the protective cap structure to expose a portion of at least one of the source region and the drain region. A conductive fill is then formed in the vias to provide a contact to the at least one of the source region and the drain region.

摘要翻译： 本公开提供了一种用于形成半导体器件的方法，其包括形成覆盖在衬底的沟道区上的替代栅极结构。 在衬底的源极和漏极区域上形成心轴介电层。 去除替代栅极结构以提供暴露衬底的沟道区的开口。 在包括功函数金属层的沟道区域上形成功能栅极结构。 在功能栅极结构上形成保护帽结构。 通过对保护盖结构有选择性的心轴介质层蚀刻至少一个通孔，以暴露源极区域和漏极区域中的至少一个的一部分。 然后在通孔中形成导电填充物以提供与源极区域和漏极区域中的至少一个的接触。

公开(公告)号：US09536985B2

公开(公告)日：2017-01-03

申请号：US14499356

申请日：2014-09-29

申请人： GLOBALFOUNDRIES INC.

发明人： Michael P. Chudzik ,  Brian J. Greene ,  Eric C. T. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Renee T. Mo ,  Yinxiao Yang

IPC分类号： H01L29/66

CPC分类号： H01L29/66795 ,  H01L29/7848

摘要： A method for producing a semiconductor structure, as well as a semiconductor structure, that uses a partial removal of an insulating layer around a semiconductor fin, and subsequently epitaxially growing an additional semiconductor material in the exposed regions, while maintaining the shape of the fin with the insulating layer.

摘要翻译： 一种用于制造半导体结构的方法以及半导体结构，其使用半导体鳍周围的绝缘层的部分去除，并且随后在暴露区域中外延生长另外的半导体材料，同时保持鳍的形状，同时保持鳍的形状 绝缘层。

公开(公告)号：US09437496B1

公开(公告)日：2016-09-06

申请号：US14727219

申请日：2015-06-01

申请人： GLOBALFOUNDRIES INC.

发明人： Michael P. Chudzik ,  Brian J. Greene ,  Edward P. Maciejewski ,  Kevin McStay ,  Shreesh Narasimha ,  Chengwen Pei ,  Werner A. Rausch

IPC分类号： H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02

CPC分类号： H01L29/66795 ,  H01L29/66545

摘要： A semiconductor device such as a FinFET includes a plurality of fins formed upon a substrate and a gate covering a portion of the fins. Diamond-shaped volumes are formed on the sidewalls of the fins by epitaxial growth which may be limited to avoid merging of the volumes or where the epitaxy volumes have merged. Because of the difficulties in managing merging of the diamond-shaped volumes, a controlled merger of the diamond-shaped volumes includes depositing an amorphous semiconductor material upon the diamond-shaped volumes and a crystallization process to crystallize the deposited semiconductor material on the diamond-shaped volumes to fabricate controllable and uniformly merged source drain.

摘要翻译： 诸如FinFET的半导体器件包括形成在衬底上的多个鳍片和覆盖鳍片的一部分的栅极。 通过外延生长在翅片的侧壁上形成菱形体积，其可以被限制以避免体积的合并或外延体积合并的位置。 由于难以管理菱形体积的合并，钻石形容积的受控合并包括在金刚石体积上沉积非晶半导体材料和结晶过程以将沉积的半导体材料结晶在菱形体上 体积来制造可控和均匀合并的源极漏极。

公开(公告)号：US09397177B2

公开(公告)日：2016-07-19

申请号：US14088462

申请日：2013-11-25

申请人： GLOBALFOUNDRIES INC.

发明人： Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L21/321

CPC分类号： H01L29/42376 ,  H01L21/28088 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

摘要： A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks.

摘要翻译： 形成半导体器件的方法包括在半导体衬底上形成第一和第二半导体结构。 第一半导体结构包括具有第一栅极长度的第一栅极沟道区，并且第二半导体结构包括具有大于第一栅极长度的第二栅极长度的第二栅极沟道区。 该方法还包括在第一栅极沟道区域中形成的第一栅极空隙和形成在第二栅极沟道区域处的第二栅极空穴中沉积功函数金属层。 该方法还包括在功函数金属层上沉积半导体掩模层，同时蚀刻位于第一和第二栅极沟道区的硅掩模层，以重新暴露第一和第二栅极空隙。 在第一和第二栅极空隙中沉积低电阻金属以形成低电阻金属栅极叠层。