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    EEPROM with improved circuit performance and reduced cell size
    51.
    发明授权
    EEPROM with improved circuit performance and reduced cell size 失效
    EEPROM具有改进的电路性能和减小的电池尺寸

    公开(公告)号：US06963503B1

    公开(公告)日：2005-11-08

    申请号：US10618280

    申请日：2003-07-11

    申请人： Irfan Rahim ,  Veenu Shekhar

    发明人： Irfan Rahim ,  Veenu Shekhar

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0441 ,  G11C2216/10 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11558

    摘要： An EEPROM cell with reduced cell size and improved circuit performance includes a high-voltage (HV) capacitor, a low-voltage (LV) read path, and an HV write path, wherein either the HV capacitor is placed between the LV read path and the HV write path or the HV write path is placed between the LV read path and the HV capacitor. The EEPROM cell also includes a native floating-gate (FG) transistor in the LV read path. Using a native FG transistor in the LV read path results in further reduction in the cell size and improved circuit performance of the EEPROM cell.

    摘要翻译： 具有减小的单元尺寸和改进的电路性能的EEPROM单元包括高压（HV）电容器，低电压（LV）读取路径和HV写入路径，其中HV电容器放置在LV读取路径和 HV写入路径或HV写入路径位于LV读取路径和HV电容器之间。 EEPROM单元还包括LV读取路径中的原生浮栅（FG）晶体管。 在LV读取路径中使用本机FG晶体管导致EEPROM单元的单元尺寸的进一步减小和电路性能的提高。

    Non-volatile memory cell having a high coupling ratio
    52.
    发明授权
    Non-volatile memory cell having a high coupling ratio 失效
    具有高耦合比的非易失性存储单元

    公开(公告)号：US6069382A

    公开(公告)日：2000-05-30

    申请号：US22222

    申请日：1998-02-11

    申请人： Irfan Rahim

    发明人： Irfan Rahim

    IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/788

    CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L29/42324

    摘要： A non-volatile memory cell includes a floating gate having a bottom surface in contact with a tunnel layer formed on the substrate, a top surface, and sidewall surfaces oriented along the bitline direction and along the wordline direction of the memory cell. A dielectric layer covers at least a portion of the top surface and covers at least a portion of the surfaces oriented along the bitline and wordline directions. A control gate overlaps the floating gate over substantially all of its surface area. A plurality of self-aligned sidewall spacers are provided, disposed against at least the dielectric layer and the control gate sidewalls. By overlapping the control gate over the floating gate, a greater surface area is made available for charge storage and/or for increasing the coupling ratio of the memory cell. This allows the width of wing structures to be decreased, while maintaining a high coupling ratio. This greater surface area, by increasing the coupling ratio of the memory cell, also allows the use of low programming and erase voltages. Charge retention and coupling are also increased by substantially overlapping or encapsulating the floating gate by the control gate, thus keeping it isolated from other structures, such as sidewall spacers.

    摘要翻译： 非易失性存储单元包括具有与形成在基板上的隧道层接触的底表面的浮动栅极，顶表面和沿着位线方向并沿着存储单元的字线方向定向的侧壁表面。 电介质层覆盖顶表面的至少一部分并且覆盖沿着位线和字线方向定向的表面的至少一部分。 控制栅极在其基本上所有的表面区域上与浮动栅极重叠。 提供了多个自对准侧壁间隔物，其设置成抵靠至少介电层和控制栅极侧壁。 通过在浮动栅极上重叠控制栅极，使更大的表面积可用于电荷存储和/或用于增加存储器单元的耦合比。 这允许翼结构的宽度减小，同时保持高耦合比。 通过增加存储单元的耦合比，该较大的表面积也允许使用低编程和擦除电压。 电荷保持和耦合也通过由控制栅极基本上重叠或封装浮置栅极而增加，从而使其与诸如侧壁间隔物的其它结构隔离。

    APPARATUS FOR IMPROVING RELIABILITY OF ELECTRONIC CIRCUITRY AND ASSOCIATED METHODS
    53.
    发明申请
    APPARATUS FOR IMPROVING RELIABILITY OF ELECTRONIC CIRCUITRY AND ASSOCIATED METHODS 有权
    提高电子电路可靠性和相关方法的设备

    公开(公告)号：US20130002287A1

    公开(公告)日：2013-01-03

    申请号：US13174599

    申请日：2011-06-30

    申请人： Bruce B. Pedersen ,  Irfan Rahim

    发明人： Bruce B. Pedersen ,  Irfan Rahim

    IPC分类号： H03K19/003 ,  H01L35/00 ,  H01L41/00 ,  H01L25/00

    CPC分类号： H03K19/17752 ,  H03K19/003

    摘要： In an exemplary embodiment, an apparatus includes a first set of circuit elements and a second set of circuit elements. The first set of circuit elements is used in a first configuration of the apparatus, and the second set of circuit elements is used in a second configuration of the apparatus. The first configuration of the apparatus is switched to the second configuration of the apparatus in order to improve reliability of the apparatus.

    摘要翻译： 在示例性实施例中，装置包括第一组电路元件和第二组电路元件。 第一组电路元件用于装置的第一配置，并且第二组电路元件用于装置的第二配置。 该设备的第一配置被切换到设备的第二配置，以便提高设备的可靠性。

    Electrostatic discharge protection circuit
    56.
    发明授权
    Electrostatic discharge protection circuit 有权
    静电放电保护电路

    公开(公告)号：US07400480B2

    公开(公告)日：2008-07-15

    申请号：US11890933

    申请日：2007-08-07

    申请人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin S. Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie T. Tran

    发明人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin S. Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie T. Tran

    IPC分类号： H02H3/22

    CPC分类号： H01L27/0266 ,  H01L27/0251

    摘要： Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.

    摘要翻译： 提供具有诸如可编程多晶硅保险丝等敏感电路的集成电路。 提供静电放电（ESD）保护电路，防止在存在静电放电事件时敏感电路的损坏或不期望的编程。 静电放电保护电路可以具有电源ESD器件，其将敏感电路两端的电压电平限制到最大电压，并且当暴露于ESD信号时，其将电流从敏感电路吸取。 静电放电保护电路还可以具有ESD余量电路，当在敏感电路上施加最大电压时，该余量电路有助于防止电流流经敏感电路。

    Method and apparatus for reducing charge loss in a nonvolatile memory cell
    57.
    发明授权
    Method and apparatus for reducing charge loss in a nonvolatile memory cell 有权
    用于减少非易失性存储单元中的电荷损失的方法和装置

    公开(公告)号：US07291546B1

    公开(公告)日：2007-11-06

    申请号：US10872618

    申请日：2004-06-21

    申请人： Irfan Rahim ,  Fangyun Richter

    发明人： Irfan Rahim ,  Fangyun Richter

    IPC分类号： H01L21/8247

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825

    摘要： A method of fabricating a non-volatile memory cell on a semiconductor substrate is disclosed. An area of a first region of the semiconductor substrate designated for a layer of floating polysilicon is blocked while a second region of the semiconductor substrate designated for a layer of non-floating polysilicon is exposed. Exposed regions of the semiconductor substrate are doped with charges.

    摘要翻译： 公开了一种在半导体衬底上制造非易失性存储单元的方法。 指定用于浮动多晶硅层的半导体衬底的第一区域的区域被封闭，而指定用于非浮动多晶硅层的第二半导体衬底的区域被暴露。 半导体衬底的暴露区域掺杂有电荷。

    Methods for optimizing programmable logic device performance by reducing congestion
    58.
    发明授权
    Methods for optimizing programmable logic device performance by reducing congestion 有权
    通过减少拥塞来优化可编程逻辑器件性能的方法

    公开(公告)号：US07210115B1

    公开(公告)日：2007-04-24

    申请号：US10884612

    申请日：2004-07-02

    申请人： Irfan Rahim ,  Yow-Juang (Bill) Liu

    发明人： Irfan Rahim ,  Yow-Juang (Bill) Liu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F17/5036

    摘要： Methods and apparatus for designing and producing programmable logic devices are provided. A logic design system may be used to analyze various implementations of a desired logic design for a programmable logic device integrated circuit. The logic design system may be used to produce configuration data for the programmable logic device in accordance with an optimized implementation. A logic circuit for a programmable logic device can be analyzed by taking into account the effects of hotspots, power supply voltage drops, and signal congestion on device performance. By modeling the performance of transistors and other components using position-dependent and signal-dependent variables such as temperature, voltage, and capacitance, the effects of congestion on device performance can be characterized and an optimum implementation of the logic design in a programmable logic device can be obtained.

    摘要翻译： 提供了设计和制造可编程逻辑器件的方法和设备。 可以使用逻辑设计系统来分析用于可编程逻辑器件集成电路的期望逻辑设计的各种实现。 逻辑设计系统可以用于根据优化的实现来产生可编程逻辑器件的配置数据。 可以通过考虑热点，电源电压降和信号拥塞对器件性能的影响来分析可编程逻辑器件的逻辑电路。 通过使用位置相关和信号相关变量（如温度，电压和电容）对晶体管和其他组件的性能进行建模，可以对设备性能拥塞的影响进行表征，并在可编程逻辑器件中实现逻辑设计 可以获得。

    High performance lateral bipolar transistor
    60.
    发明授权
    High performance lateral bipolar transistor 有权
    高性能横向双极晶体管

    公开(公告)号：US07173320B1

    公开(公告)日：2007-02-06

    申请号：US10427777

    申请日：2003-04-30

    申请人： Irfan Rahim

    发明人： Irfan Rahim

    IPC分类号： H01L29/00 ,  H01L29/82 ,  H01L43/00 ,  H01L27/082

    CPC分类号： H01L29/7394 ,  H01L29/0696 ,  H01L29/7317 ,  H01L29/78624

    摘要： A lateral bipolar transistor includes an emitter region, a base region, a collector region, and a gate disposed over the base region. A bias line is connected to the gate for applying a bias voltage thereto during operation of the transistor. The polarity of the bias voltage is such as to create an accumulation layer in the base under the gate. The accumulation layer provides a low-resistance path for the transistor base current, thus reducing the base resistance of the transistor.

    摘要翻译： 横向双极晶体管包括发射极区域，基极区域，集电极区域和设置在基极区域上的栅极。 偏置线连接到栅极，以在晶体管的工作期间施加偏置电压。 偏置电压的极性使得在栅极下方的基极中产生积聚层。 累积层为晶体管基极电流提供低电阻通路，从而降低晶体管的基极电阻。