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162 条记录 (耗时 0.038 秒)

    Photo-sensor and pixel array with backside illumination and method of forming the photo-sensor
    52.
    发明授权
    Photo-sensor and pixel array with backside illumination and method of forming the photo-sensor 有权
    具有背面照明的光电传感器和像素阵列以及形成光电传感器的方法

    公开(公告)号：US07586139B2

    公开(公告)日：2009-09-08

    申请号：US11276218

    申请日：2006-02-17

    申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Alan Loiseau ,  Richard J. Rassel

    发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Alan Loiseau ,  Richard J. Rassel

    IPC分类号： H01L31/062 ,  H01L21/00

    CPC分类号： H01L27/14643 ,  H01L27/14621 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14689

    摘要： An imaging sensor with an array of FET pixels and method of forming the imaging sensor. Each pixel is a semiconductor island, e.g., N-type silicon on a Silicon on insulator (SOI) wafer. FETs are formed in one photodiode electrode, e.g., a P-well cathode. A color filter may be attached to an opposite surface of island. A protective layer (e.g., glass or quartz) or window is fixed to the pixel array at the color filters. The image sensor may be illuminated from the backside with cell wiring above the cell. So, an optical signal passes through the protective layer is filtered by the color filters and selectively sensed by a corresponding photo-sensor.

    摘要翻译： 具有FET像素阵列的成像传感器和形成成像传感器的方法。 每个像素是半导体岛，例如绝缘体上硅（SOI）晶片上的N型硅。 FET形成在一个光电二极管电极中，例如P阱阴极。 滤色器可以附接到岛的相对表面。 保护层（例如，玻璃或石英）或窗口在滤色器处固定到像素阵列。 图像传感器可以从背面照亮，电池布线在电池单元上方。 因此，通过保护层的光学信号被滤色器过滤并被相应的光电传感器选择性地感测。

    CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom
    57.
    发明授权
    CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom 有权
    具有Cu布线的CMOS成像器和从其中消除高反射率界面的方法

    公开(公告)号：US07342268B2

    公开(公告)日：2008-03-11

    申请号：US10905277

    申请日：2004-12-23

    申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

    发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

    IPC分类号： H01L31/062

    CPC分类号： H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

    摘要： An image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

    摘要翻译： 一种图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光敏度的像素阵列。 图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

    LOW LAG TRANSFER GATE DEVICE
    59.
    发明申请
    LOW LAG TRANSFER GATE DEVICE 有权
    LOW LAG传输闸门装置

    公开(公告)号：US20090180010A1

    公开(公告)日：2009-07-16

    申请号：US12013826

    申请日：2008-01-14

    申请人： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan

    发明人： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan

    IPC分类号： H04N3/14 ,  H01L31/18

    CPC分类号： H01L31/103 ,  H04N5/353 ,  H04N5/374 ,  H04N5/3745

    摘要： A method of forming a CMOS active pixel sensor (APS) cell structure having at least one transfer gate device and method of operation. A first transfer gate device comprises a diodic or split transfer gate conductor structure having a first doped region of first conductivity type material and a second doped region of a second conductivity type material. A photosensing device is formed adjacent the first doped region for collecting charge carriers in response to light incident thereto, and, a diffusion region of a second conductivity type material is formed at or below the substrate surface adjacent the second doped region of the transfer gate device for receiving charges transferred from the photosensing device while preventing spillback of charges to the photosensing device upon timed voltage bias to the diodic or split transfer gate conductor structure. Alternately, an intermediate charge storage device and second transfer gate device may be provided which may first temporarily receive charge carriers from the photosensing device, and, upon activating the second transfer gate device in a further timed fashion, read out the charge stored at the intermediate charge storage device for transfer to the second transfer gate device while preventing spillback of charges to the photosensing device. The APS cell structure is further adapted for a global shutter mode of operation, and further comprises a light shield element is further provided to ensure no light reaches the photosensing and charge storage devices during charge transfer operation.

    摘要翻译： 一种形成具有至少一个传输栅极器件和操作方法的CMOS有源像素传感器（APS）单元结构的方法。 第一传输栅极器件包括具有第一导电类型材料的第一掺杂区域和第二导电类型材料的第二掺杂区域的二极或分裂传输栅极导体结构。 光敏装置形成在第一掺杂区域附近，用于响应于入射到其上的光而收集电荷载流子，并且第二导电类型材料的扩散区域形成在与传输栅极器件的第二掺杂区域相邻的衬底表面处或下方 用于接收从光敏装置转移的电荷，同时防止在针对二极或分离转移栅极导体结构的定时电压偏压时对光敏装置的电荷溢出。 或者，可以提供中间电荷存储装置和第二传输门装置，其可以首先临时从光敏装置接收电荷载体，并且在以另外的定时方式激活第二传输门装置时，读出存储在中间 电荷存储装置，用于传送到第二传输门装置，同时防止电荷向光感器件溢出。 APS单元结构进一步适用于全局快门操作模式，并且进一步包括遮光元件，以在电荷转移操作期间确保没有光到达光敏和电荷存储装置。

    Multiple precipitation doping process
    60.
    发明授权
    Multiple precipitation doping process 失效
    多重沉淀掺杂工艺

    公开(公告)号：US06300228B1

    公开(公告)日：2001-10-09

    申请号：US09386089

    申请日：1999-08-30

    申请人： James W. Adkisson ,  James A. Bruce ,  John J. Ellis-Monaghan ,  Randy W. Mann ,  Edward J. Nowak ,  Kirk D. Peterson

    发明人： James W. Adkisson ,  James A. Bruce ,  John J. Ellis-Monaghan ,  Randy W. Mann ,  Edward J. Nowak ,  Kirk D. Peterson

    IPC分类号： H01L2122

    CPC分类号： H01L21/268 ,  H01L21/0455 ,  H01L21/2255

    摘要： A multiple precipitation doping process for doping a semiconductor substrate (30) starts with forming an amorphous region (32) in the substrate (30). Through multiple laser exposures, multiple dopant precipitation films (52, 53) are formed on corresponding portions (34, 37) of the major surface (31) of the substrate (30) overlying the amorphous region (32). The substrate (30) is then annealed. The annealing process melts the amorphous region (32) and allows the dopants precipitated on the major surface (31) to diffuse into the substrate (30). The annealing process also crystallizes the semiconductor material the amorphous region (32). The substrate (30) becomes a single crystal semiconductor substrate with multiple doped regions (54, 57) therein. The depth of the doped regions (54, 57) is substantially equal to the depth of the amorphous region (32) before annealing.

    摘要翻译： 用于掺杂半导体衬底（30）的多次沉淀掺杂工艺从在衬底（30）中形成无定形区域（32）开始。 通过多次激光曝光，在覆盖非晶区域（32）的衬底（30）的主表面（31）的相应部分（34,37）上形成多个掺杂剂沉淀膜（52,53）。 然后将衬底（30）退火。 退火过程熔化非晶区域（32）并且允许沉淀在主表面（31）上的掺杂剂扩散到衬底（30）中。 退火过程也使非晶区域（32）半导体材料结晶。 基板（30）成为具有多个掺杂区域（54,57）的单晶半导体基板。 掺杂区域（54,57）的深度基本上等于退火前非晶区域（32）的深度。