Semiconductor memory device
    53.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号:US20060203586A1

    公开(公告)日:2006-09-14

    申请号:US11360681

    申请日:2006-02-24

    IPC分类号: G11C7/00

    摘要: A memory cell MC includes nMOS transistors for a transfer gate configured to be paired with each other, and one capacitor for data storage connected to the nMOS transistor. A gate electrode of the nMOS transistor is connected to a word line WL, and a drain is connected to a bit line BL. A gate electrode of the nMOS transistor is connected to a word line /WL, and a drain and a source are connected to a ground. The capacitor is connected between a source of the nMOS transistor and the ground. A Y selector circuit is connected between a differential bit line BL, /BL and a differential data line DL, /DL. The Y selector circuit has two pairs of nMOS transistors configured to be paired transistors, respectively.

    摘要翻译: 存储单元MC包括用于被配置为彼此配对的传输门的nMOS晶体管,以及连接到nMOS晶体管的一个用于数据存储的电容器。 nMOS晶体管的栅电极连接到字线WL,漏极连接到位线BL。 nMOS晶体管的栅电极连接到字线/ WL,漏极和源极连接到地。 电容器连接在nMOS晶体管的源极和地之间。 Y选择电路连接在差分位线BL,/ BL和差分数据线DL / DL之间。 Y选择器电路具有分别配置为成对晶体管的两对nMOS晶体管。

    Wiring structure for transmission line having grooved conductors
    54.
    发明授权
    Wiring structure for transmission line having grooved conductors 失效
    具有槽导体的传输线的接线结构

    公开(公告)号:US06914502B2

    公开(公告)日:2005-07-05

    申请号:US09988017

    申请日:2001-11-16

    CPC分类号: H01P3/081 H05K1/0237

    摘要: A wiring structure for a transmission line has a ground line (2) and a signal line (1). The signal line (1) is disposed so as to face the ground line (2) through a dielectric (3). A surface of the signal line (1) facing the ground line (2) has a groove extending in the transmission direction. A surface of the ground line (2) facing the signal line (1) also has a groove extending in the transmission direction. The grooves restrain that electromagnetic induction is caused in the signal line (1) due to an electromagnetic field generated by other adjacent signal lines (1).

    摘要翻译: 传输线的布线结构具有接地线(2)和信号线(1)。 信号线(1)通过电介质(3)设置成与地线(2)相对。 面向地线(2)的信号线(1)的表面具有在传输方向上延伸的凹槽。 接地线(2)的面向信号线(1)的表面还具有沿传输方向延伸的凹槽。 沟槽限制了由于其他相邻信号线(1)产生的电磁场而在信号线(1)中引起电磁感应。

    Signal transmission system, and signal transmission line
    55.
    发明申请
    Signal transmission system, and signal transmission line 有权
    信号传输系统和信号传输线

    公开(公告)号:US20050040846A1

    公开(公告)日:2005-02-24

    申请号:US10898874

    申请日:2004-07-26

    CPC分类号: H04L25/08 H03K17/04106

    摘要: To transmit a high-speed digital signal of several tens GHz via a differential line by connecting a differential line referring to the ground to differential lines not referring to the ground, there is provided a signal transmission system which transmits a digital signal between circuit blocks via a signal transmission line, each of the circuit blocks basically including a functional circuit, a reception/transmission circuit formed separately from the functional circuit and an impedance-matched transmission line (115) formed between reception and transmission ends of the reception/transmission circuit; a differential line (105) referring to the ground (110), led out from a differential output driver, being formed from differential signal lines disposed symmetrically with respect to the ground (110) in the circuit block, only differential pair lines (111, 112) not referring to the ground being extended directly from the differential signal lines disposed symmetrically with respect to the ground in the signal transmission line (115).

    摘要翻译: 通过将差分线连接到不涉及地面的差分线,通过差分线路传输数十GHz的高速数字信号,提供了一种信号传输系统,其通过电路块之间的数字信号经由 信号传输线,每个电路块基本上包括功能电路,与功能电路分开形成的接收/发送电路和形成在接收/发送电路的接收和发送端之间的阻抗匹配传输线路(115); 从差分输出驱动器引出的对地(110)的差分线(105)由相对于电路块中的接地(110)对称设置的差分信号线形成,仅差分对线(111, 112),而不是直接从在信号传输线路(115)中相对于地面对称设置的差动信号线延伸的地面。

    Semiconductor integrated circuit having switching transistors and varactors
    56.
    发明授权
    Semiconductor integrated circuit having switching transistors and varactors 有权
    具有开关晶体管和变容二极管的半导体集成电路

    公开(公告)号:US06731153B2

    公开(公告)日:2004-05-04

    申请号:US09963500

    申请日:2001-09-27

    IPC分类号: H03K1704

    CPC分类号: H03K19/01707

    摘要: A CMOS line driver is made up of p- and nMOS transistors. A pMOS varactor is interposed between the source of the pMOS transistor and a power supply, while an nMOS varactor is interposed between the source of the nMOS transistor and ground. The sizes of each of these MOS varactors may be the same as those of the p- or nMOS transistor. Alternatively, each of these MOS varactors may have a channel area twice greater than that of the p- or nMOS transistor. The inverted version of a signal input to the line driver is supplied to the gates of the MOS varactors. In this manner, the MOS transistors, making up the line driver, can switch at a high speed.

    摘要翻译: CMOS线路驱动器由p-和nMOS晶体管组成。 pMOS变容二极管介于pMOS晶体管的源极和电源之间,而nMOS变容二极管插在nMOS晶体管的源极和地之间。 这些MOS可变电抗器的尺寸可以与p型或nMOS晶体管的尺寸相同。 或者,这些MOS变容二极管中的每一个可以具有比p型或nMOS晶体管的沟道面积的两倍的沟道面积。 将输入到线路驱动器的信号的反相形式提供给MOS可变电抗器的栅极。 以这种方式,构成线路驱动器的MOS晶体管可以高速切换。

    Electronic device
    57.
    发明授权

    公开(公告)号:US06522173B1

    公开(公告)日:2003-02-18

    申请号:US09280652

    申请日:1999-03-29

    申请人: Kanji Otsuka

    发明人: Kanji Otsuka

    IPC分类号: H01P308

    摘要: An electronic device includes a wiring board, and at least one pair of signal lines that is provided on the wiring board in parallel and has an equal length. A chip is mounted on the wiring board and includes at least one differential driver which outputs complementary digital transmit signals to said at least one of lines. A pair of power system lines is provided to supply first and second power supply voltages to the above-mentioned at least one differential driver. The power system lines are parallel to each other and have an equal length.