公开(公告)号：US5534072A

公开(公告)日：1996-07-09

申请号：US77687

申请日：1993-06-16

申请人： Shigeru Mizuno ,  Yoshihiro Katsumata ,  Nobuyuki Takahashi

发明人： Shigeru Mizuno ,  Yoshihiro Katsumata ,  Nobuyuki Takahashi

IPC分类号： C23C16/44 ,  C23C16/455 ,  C23C16/458 ,  C23C16/54 ,  C23C16/00

CPC分类号： C23C16/45519 ,  C23C16/4401 ,  C23C16/45521 ,  C23C16/4585 ,  C23C16/54 ,  Y10S414/135 ,  Y10S438/908

摘要： In a CVD processing system for depositing a blanket tungsten film, a distinct shadow is formed without causing any micro-peeling when the substrate fixture is separated from the substrate so as to prevent any blanket tungsten from being deposited on SiO.sub.2, thus reducing the occurrence of fine dust particles. A CVD processing system for depositing a blanket tungsten film, includes a susceptor (4); a ring chuck (9) for affixing the peripheral portion of a substrate (3) on the susceptor; reactive gas supply mechanisms (17, 18 and 19) for supplying reactive gas; and an exhaust mechanism (2) for exhausting unreacted gas and the like, wherein: the ring chuck has at least three point contact members (10) in contact with the peripheral portion of the substrate; the point contact members are provided at positions outside the inner periphery of the ring chuck; a gap (11) is formed at the point contact members between the ring chuck and the substrate; and purge gas supply mechanisms (20 and 21) are provided to blow off purge gas through the gap in order to prevent reactive gas from entering the gap (11). A ratio of the size of the gap to the flow rate of purge gas is set to such an optimum value as to satisfy a condition in which the position of the peripheral portion of the thin film coincides with the position of the inner periphery of the ring chuck.

摘要翻译： 在用于沉积覆盖钨膜的CVD处理系统中，当衬底夹具与衬底分离时，形成不同的阴影，而不会发生任何微剥离，以防止任何覆盖的钨沉积在SiO 2上，从而减少 细尘粒子。 一种用于沉积覆盖钨膜的CVD处理系统，包括基座（4）; 环形卡盘（9），用于将基板（3）的周边部分固定在基座上; 用于供应反应性气体的反应气体供应机构（17,18和19） 以及用于排出未反应气体等的排气机构（2），其中：所述环卡盘具有与所述基板的周边部分接触的至少三点接触构件（10） 点接触构件设置在环卡盘的内周的外侧的位置; 在环卡盘和基板之间的点接触构件处形成间隙（11）; 并且提供吹扫气体供给机构（20和21）以吹扫通过间隙的吹扫气体，以防止反应性气体进入间隙（11）。 将间隙尺寸与吹扫气体的流量的比率设定为最佳值，以满足薄膜的周边部分的位置与环的内周的位置一致的条件 卡盘

公开(公告)号：US08372739B2

公开(公告)日：2013-02-12

申请号：US11691167

申请日：2007-03-26

申请人： Tadahiro Ishizaka ,  Satohiko Hoshino ,  Kuzuhiro Hamamoto ,  Shigeru Mizuno ,  Yasushi Mizusawa

发明人： Tadahiro Ishizaka ,  Satohiko Hoshino ,  Kuzuhiro Hamamoto ,  Shigeru Mizuno ,  Yasushi Mizusawa

IPC分类号： H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure for an integrated circuit and method of forming the interconnect structure. The method includes depositing a metallic layer containing a reactive metal in an interconnect opening formed within a dielectric material containing a dielectric reactant element, thermally reacting at least a portion of the metallic layer with at least a portion of the dielectric material to form a diffusion barrier primarily containing a compound of the reactive metal from the metallic layer and the dielectric reactant element from the dielectric material, and filling the interconnect opening with Cu metal, where the diffusion barrier surrounds the Cu metal within the opening. The reactive metal can be Co, Ru, Mo, W, or Ir, or a combination thereof. The interconnect opening can be a trench, a via, or a dual damascene opening.

摘要翻译： 用于集成电路的互连结构和形成互连结构的方法。 该方法包括在包含介电反应物元件的电介质材料中形成的互连开口中沉积含有活性金属的金属层，使金属层的至少一部分与电介质材料的至少一部分热反应形成扩散阻挡层 主要包含来自金属层的反应性金属的化合物和来自电介质材料的介电反应物元件，并且用Cu金属填充互连开口，其中扩散阻挡层围绕开口内的Cu金属。 反应性金属可以是Co，Ru，Mo，W或Ir，或它们的组合。 互连开口可以是沟槽，通孔或双镶嵌开口。

公开(公告)号：US08076241B2

公开(公告)日：2011-12-13

申请号：US12571162

申请日：2009-09-30

申请人： Frank M. Cerio, Jr. ,  Shigeru Mizuno ,  Jonathan Reid ,  Thomas Ponnuswamy

发明人： Frank M. Cerio, Jr. ,  Shigeru Mizuno ,  Jonathan Reid ,  Thomas Ponnuswamy

IPC分类号： H01L21/44

CPC分类号： C23C18/165 ,  C23C18/161 ,  C23C18/1651 ,  C23C18/1692 ,  C23C18/38 ,  C25D5/02 ,  C25D5/10 ,  C25D5/38 ,  C25D5/50 ,  H01L21/28556 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76883

摘要： Methods are provided for multi-step Cu metal plating on a continuous Ru metal film in recessed features found in advanced integrated circuits. The use of a continuous Ru metal film prevents formation of undesirable micro-voids during Cu metal filling of high-aspect-ratio recessed features, such as trenches and vias, and enables formation of large Cu metal grains that include a continuous Cu metal layer plated onto the continuous Ru metal film. The large Cu grains lower the electrical resistivity of the Cu filled recessed features and increase the reliability of the integrated circuit.

摘要翻译： 提供了在先进集成电路中发现的凹陷特征中的连续Ru金属膜上的多步Cu金属电镀方法。 使用连续的Ru金属膜可防止在高纵横比凹陷特征（例如沟槽和通孔）的Cu金属填充期间形成不期望的微孔，并且能够形成大的Cu金属晶粒，其包括连续的Cu金属层电镀 到连续的Ru金属膜上。 大的Cu晶粒降低了Cu填充凹陷特征的电阻率，增加了集成电路的可靠性。

公开(公告)号：US07846841B2

公开(公告)日：2010-12-07

申请号：US12242900

申请日：2008-09-30

申请人： Tadahiro Ishizaka ,  Shigeru Mizuno ,  Miho Jomen

发明人： Tadahiro Ishizaka ,  Shigeru Mizuno ,  Miho Jomen

IPC分类号： H01L21/44

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/02074 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method is provided for integrating cobalt nitride cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt nitride cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k dielectric regions, and selectively forming a cobalt nitride cap layer on the Cu paths relative to the low-k dielectric regions.

摘要翻译： 提供了一种用于将氮化钴盖层整合到半导体器件的制造中以改善铜（Cu）金属中的电迁移和应力迁移的方法。 一个实施例包括提供包含形成在低k材料中的凹陷特征的图案化衬底和在特征底部的第一金属化层，在第一金属化层上形成氮化钴覆盖层，在凹陷特征中沉积阻挡层 包括在低k电介质材料和第一钴金属帽层上，并用Cu金属填充凹陷特征。 另一个实施例包括提供具有Cu路径和低k电介质区域的基本平坦表面的图案化衬底，以及相对于低k电介质区域在Cu路径上选择性地形成氮化钴覆盖层。

公开(公告)号：US07807561B2

公开(公告)日：2010-10-05

申请号：US12175650

申请日：2008-07-18

申请人： Shigeru Mizuno ,  Takashi Kurihara ,  Akinori Shiraishi ,  Kei Murayama ,  Mitsutoshi Higashi

发明人： Shigeru Mizuno ,  Takashi Kurihara ,  Akinori Shiraishi ,  Kei Murayama ,  Mitsutoshi Higashi

IPC分类号： H01L21/44

CPC分类号： H01L24/85 ,  H01L21/6835 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/76152 ,  H01L2224/78 ,  H01L2224/85001 ,  H01L2225/06551 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/4554

摘要： After plural semiconductor elements are stacked to form a stacked body P, side wirings are formed on the side surface of the stacked body P, thereby manufacturing a semiconductor apparatus in which the respective semiconductor elements are electrically connected to one another. In this case, as the semiconductor element, a semiconductor element 10 is employed in which a gold wire 16 with its one end connected to an electrode terminal of the semiconductor element is extended out to the side surface. A conductive paste 36 containing conductive particles applied over a predetermined length of a transferring wire 30 is transferred to the side surface of the stacked body P so that the gold wires 16 extended out to the side surfaces of the semiconductor elements 10, 10, 10 are connected, thereby forming the side wirings.

摘要翻译： 在堆叠多个半导体元件以形成堆叠体P之后，在层叠体P的侧表面上形成侧布线，从而制造其中各个半导体元件彼此电连接的半导体器件。 在这种情况下，作为半导体元件，采用半导体元件10，其一端与半导体元件的电极端子连接的金线16延伸到侧面。 包含施加在传输线30的预定长度上的导电颗粒的导电膏36被转移到层叠体P的侧表面，使得延伸到半导体元件10,10,10的侧表面的金线16 连接，从而形成侧面布线。

公开(公告)号：US07799681B2

公开(公告)日：2010-09-21

申请号：US12173814

申请日：2008-07-15

申请人： Kenji Suzuki ,  Frank M. Cerio, Jr. ,  Miho Jomen ,  Shigeru Mizuno ,  Yasushi Mizusawa ,  Tadahiro Ishizaka

发明人： Kenji Suzuki ,  Frank M. Cerio, Jr. ,  Miho Jomen ,  Shigeru Mizuno ,  Yasushi Mizusawa ,  Tadahiro Ishizaka

IPC分类号： H01L21/44

CPC分类号： H01L21/76849 ,  C23C16/02 ,  C23C16/16 ,  H01L21/02068 ,  H01L21/28562 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76868 ,  H01L21/76883

摘要： A method for integrating ruthenium (Ru) metal cap layers and modified Ru metal cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration (EM) and stress migration (SM) in bulk Cu metal. In one embodiment, the method includes providing a planarized patterned substrate containing a Cu metal surface and a dielectric layer surface, depositing first Ru metal on the Cu metal surface, and depositing additional Ru metal on the dielectric layer surface, where the amount of the additional Ru metal is less than the amount of the first Ru metal. The method further includes at least substantially removing the additional Ru metal from the dielectric layer surface to improve the selective formation of a Ru metal cap layer on the Cu metal surface. Other embodiments further include incorporating one or more types of modifier elements into the dielectric layer surface, the Cu metal surface, the Ru metal cap layer, or a combination thereof.

摘要翻译： 将钌（Ru）金属盖层和改性的Ru金属覆盖层整合到半导体器件的铜（Cu）金属化中以改善块状Cu金属中的电迁移（EM）和应力迁移（SM）的方法。 在一个实施例中，该方法包括提供包含Cu金属表面和电介质层表面的平坦化图案化衬底，在Cu金属表面上沉积第一Ru金属，以及在电介质层表面上沉积额外的Ru金属，其中额外的量 Ru金属少于第一Ru金属的量。 该方法还包括从电介质层表面至少基本上去除额外的Ru金属，以改善在Cu金属表面上的Ru金属覆盖层的选择性形成。 其他实施例还包括将一种或多种类型的改性剂元素结合到电介质层表面，Cu金属表面，Ru金属覆盖层或其组合中。

公开(公告)号：US07777349B2

公开(公告)日：2010-08-17

申请号：US12175689

申请日：2008-07-18

申请人： Kei Murayama ,  Shigeru Mizuno ,  Takashi Kurihara ,  Akinori Shiraishi ,  Mitsutoshi Higashi

发明人： Kei Murayama ,  Shigeru Mizuno ,  Takashi Kurihara ,  Akinori Shiraishi ,  Mitsutoshi Higashi

IPC分类号： H01L23/48

CPC分类号： H01L29/0657 ,  H01L21/6835 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/82 ,  H01L24/85 ,  H01L24/91 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/73265 ,  H01L2224/76152 ,  H01L2224/78301 ,  H01L2224/85001 ,  H01L2224/85181 ,  H01L2225/06551 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10157 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A plurality of quadrilateral-shaped semiconductor elements are stacked on the one surface of a circuit substrate. A side surface wiring for making electrical connection between each of the electrode terminals of the semiconductor elements and a pad formed on the circuit substrate is formed by applying a conductive paste containing conductive particles. A metal wire whose one end is connected to the electrode terminal is extended along a tapered surface formed by cutting off an edge of the electrode terminal surface on which the electrode terminal is formed among edges formed along each of the sides of the semiconductor element. At least a part of the metal wire extended from each of the electrode terminals of the semiconductor elements to the tapered surface is electrically connected to the side surface wiring.

摘要翻译： 多个四边形半导体元件堆叠在电路基板的一个表面上。 通过涂布含有导电性粒子的导电性糊料，形成用于在半导体元件的各电极端子与电路基板上形成的焊盘之间进行电连接的侧面配线。 其一端连接到电极端子的金属线沿着沿着半导体元件的每一侧形成的边缘之间切割形成有电极端子的电极端子表面的边缘的锥形表面延伸。 从半导体元件的每个电极端子延伸到锥形表面的金属线的至少一部分电连接到侧面布线。

公开(公告)号：US07727883B2

公开(公告)日：2010-06-01

申请号：US12242384

申请日：2008-09-30

申请人： Tadahiro Ishizaka ,  Shigeru Mizuno

发明人： Tadahiro Ishizaka ,  Shigeru Mizuno

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76873 ,  H01L23/53238

摘要： A method of forming an interconnect structure is provided. The method includes depositing a cobalt metal layer in an interconnect opening formed within a dielectric material containing a dielectric reactant element. The method further includes, in any order, thermally reacting at least a portion of the cobalt metal layer with at least a portion of the dielectric material to form a diffusion barrier containing a compound of the reactive metal from the cobalt metal layer and the dielectric reactant element from the dielectric material, and forming a cobalt nitride adhesion layer in the interconnect opening. The method further includes filling the interconnect opening with Cu metal, where the diffusion barrier and the cobalt nitride adhesion layer surround the Cu metal in the interconnect opening.

摘要翻译： 提供一种形成互连结构的方法。 该方法包括在形成在包含介电反应物元件的电介质材料内的互连开口中沉积钴金属层。 该方法还包括以任何顺序使钴金属层的至少一部分与电介质材料的至少一部分热反应形成包含来自钴金属层和介电反应物的反应性金属化合物的扩散阻挡层 元件，并且在互连开口中形成氮化钴粘合层。 该方法还包括用Cu金属填充互连开口，其中扩散阻挡层和氮化钴粘合层围绕互连开口中的Cu金属。

公开(公告)号：US07724493B2

公开(公告)日：2010-05-25

申请号：US12289207

申请日：2008-10-22

申请人： Shigeru Mizuno ,  Masahito Ishihara ,  Sunil Wickramanayaka ,  Naoki Miyazaki

发明人： Shigeru Mizuno ,  Masahito Ishihara ,  Sunil Wickramanayaka ,  Naoki Miyazaki

IPC分类号： H01T23/001

CPC分类号： H01L21/6875 ,  H01L21/6833 ,  H02N13/00

摘要： An electrostatic chuck device provided with a dielectric plate with a surface embossed to give it a plurality of projections, an electrode, and an external power source, wherein substrate supporting surfaces of the plurality of projections are covered by conductor wiring and the conductor wiring electrically connects the substrate supporting surfaces of the plurality of projections. At the time of substrate processing, when the embossed projections contact the back of the substrate, the back of the substrate and the conductor wiring is made the same in potential due to the migration of the charges, the generation of force between the back of the substrate and the conductor wiring being in contact with the same is prevented, and a rubbing state between the two is prevented. Due to this, the electrostatic chuck device reduces the generation of particles, easily and stably removes and conveys substrates, and realizes a high yield and system operating rate.

摘要翻译： 一种静电吸盘装置，其具有表面压花的电介质板，以给予多个突起，电极和外部电源，其中所述多个突起的基板支撑表面被导体布线覆盖，并且所述导体布线电连接 多个突起的基板支撑表面。 在基板处理时，当压花突起接触基板的背面时，由于电荷的迁移，基板的背面和导体布线的潜力也相同，因此在 基板和与其接触的导体布线被防止，并且防止了两者之间的摩擦状态。 由此，静电卡盘装置减少了颗粒的产生，容易且稳定地除去和输送基板，实现了高产率和系统运行速度。

公开(公告)号：US20100081275A1

公开(公告)日：2010-04-01

申请号：US12242900

申请日：2008-09-30

申请人： Tadahiro Ishizaka ,  Shigeru Mizuno ,  Miho Jomen

发明人： Tadahiro Ishizaka ,  Shigeru Mizuno ,  Miho Jomen

IPC分类号： H01L21/768

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/02074 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method is provided for integrating cobalt nitride cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt nitride cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k dielectric regions, and selectively forming a cobalt nitride cap layer on the Cu paths relative to the low-k dielectric regions.

摘要翻译： 提供了一种用于将氮化钴盖层整合到半导体器件的制造中以改善铜（Cu）金属中的电迁移和应力迁移的方法。 一个实施例包括提供包含形成在低k材料中的凹陷特征的图案化衬底和在特征底部的第一金属化层，在第一金属化层上形成氮化钴覆盖层，在凹陷特征中沉积阻挡层 包括在低k电介质材料和第一钴金属帽层上，并用Cu金属填充凹陷特征。 另一个实施例包括提供具有Cu路径和低k电介质区域的基本平坦表面的图案化衬底，以及相对于低k电介质区域在Cu路径上选择性地形成氮化钴覆盖层。