GAN vertical superjunction device structures and fabrication methods
    52.
    发明授权
    GAN vertical superjunction device structures and fabrication methods 有权
    GAN垂直超结装置结构及制造方法

    公开(公告)号:US08785975B2

    公开(公告)日:2014-07-22

    申请号:US13529822

    申请日:2012-06-21

    摘要: A semiconductor device includes a III-nitride substrate of a first conductivity type, a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate, and a first III-nitride epitaxial structure coupled to a first portion of a surface of the first III-nitride epitaxial layer. The first III-nitride epitaxial structure has a sidewall. The semiconductor device further includes a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure, a second III-nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second III-nitride epitaxial layer and a second portion of the surface of the first III-nitride epitaxial layer, and a third III-nitride epitaxial layer of a second conductivity type coupled to the second III-nitride epitaxial layer. The semiconductor device also includes one or more dielectric structures coupled to a surface of the third III-nitride epitaxial layer.

    摘要翻译: 半导体器件包括第一导电类型的III族氮化物衬底,耦合到III族氮化物衬底的第一导电类型的第一III族氮化物外延层和耦合到第一III族氮化物外延结构的第一部分 第一III族氮化物外延层的表面。 第一III族氮化物外延结构具有侧壁。 半导体器件还包括耦合到第一III族氮化物外延结构的第一导电类型的第二III族氮化物外延结构,第一导电类型的第二III族氮化物外延层耦合到第二III族氮化物外延的侧壁 层和第一III族氮化物外延层的表面的第二部分,以及耦合到第二III族氮化物外延层的第二导电类型的第三III族氮化物外延层。 半导体器件还包括耦合到第三III族氮化物外延层的表面的一个或多个电介质结构。

    GAN VERTICAL SUPERJUNCTION DEVICE STRUCTURES AND FABRICATION METHODS
    53.
    发明申请
    GAN VERTICAL SUPERJUNCTION DEVICE STRUCTURES AND FABRICATION METHODS 有权
    GAN垂直超导装置结构和制造方法

    公开(公告)号:US20130341677A1

    公开(公告)日:2013-12-26

    申请号:US13529822

    申请日:2012-06-21

    IPC分类号: H01L27/088 H01L21/8234

    摘要: A semiconductor device includes a III-nitride substrate of a first conductivity type, a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate, and a first III-nitride epitaxial structure coupled to a first portion of a surface of the first III-nitride epitaxial layer. The first III-nitride epitaxial structure has a sidewall. The semiconductor device further includes a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure, a second III-nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second III-nitride epitaxial layer and a second portion of the surface of the first III-nitride epitaxial layer, and a third III-nitride epitaxial layer of a second conductivity type coupled to the second III-nitride epitaxial layer. The semiconductor device also includes one or more dielectric structures coupled to a surface of the third III-nitride epitaxial layer.

    摘要翻译: 半导体器件包括第一导电类型的III族氮化物衬底,耦合到III族氮化物衬底的第一导电类型的第一III族氮化物外延层和耦合到第一III族氮化物外延结构的第一部分 第一III族氮化物外延层的表面。 第一III族氮化物外延结构具有侧壁。 半导体器件还包括耦合到第一III族氮化物外延结构的第一导电类型的第二III族氮化物外延结构,第一导电类型的第二III族氮化物外延层耦合到第二III族氮化物外延的侧壁 层和第一III族氮化物外延层的表面的第二部分,以及耦合到第二III族氮化物外延层的第二导电类型的第三III族氮化物外延层。 半导体器件还包括耦合到第三III族氮化物外延层的表面的一个或多个电介质结构。

    Vertical GaN JFET with gate source electrodes on regrown gate
    54.
    发明授权
    Vertical GaN JFET with gate source electrodes on regrown gate 有权
    在再生栅上具有栅极源电极的垂直GaN JFET

    公开(公告)号:US08698164B2

    公开(公告)日:2014-04-15

    申请号:US13315720

    申请日:2011-12-09

    IPC分类号: H01L29/808 H01L21/335

    摘要: A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.

    摘要翻译: 半导体结构包括具有第一表面和第二表面的GaN衬底。 GaN衬底的特征在于第一导电类型和第一掺杂剂浓度。 第一电极电耦合到GaN衬底的第二表面。 半导体结构还包括耦合到GaN衬底的第一表面的第一导电类型的第一GaN外延层和耦合到第一GaN外延层的第二导电类型的第二GaN层。 第一GaN外延层包括沟道区。 第二GaN外延层包括栅极区域和边缘端接结构。 耦合到栅极区域的第二电极和耦合到沟道区域的第三电极都设置在边缘端接结构内。

    Vertical GaN JFET with Gate Source Electrodes on Regrown Gate
    55.
    发明申请
    Vertical GaN JFET with Gate Source Electrodes on Regrown Gate 有权
    垂直GaN JFET与栅极源电极在Regrown Gate

    公开(公告)号:US20130146886A1

    公开(公告)日:2013-06-13

    申请号:US13315720

    申请日:2011-12-09

    摘要: A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.

    摘要翻译: 半导体结构包括具有第一表面和第二表面的GaN衬底。 GaN衬底的特征在于第一导电类型和第一掺杂剂浓度。 第一电极电耦合到GaN衬底的第二表面。 半导体结构还包括耦合到GaN衬底的第一表面的第一导电类型的第一GaN外延层和耦合到第一GaN外延层的第二导电类型的第二GaN层。 第一GaN外延层包括沟道区。 第二GaN外延层包括栅极区域和边缘端接结构。 耦合到栅极区域的第二电极和耦合到沟道区域的第三电极都设置在边缘端接结构内。

    Vertical GaN-based metal insulator semiconductor FET
    58.
    发明授权
    Vertical GaN-based metal insulator semiconductor FET 失效
    垂直GaN基金属绝缘体半导体FET

    公开(公告)号:US08558242B2

    公开(公告)日:2013-10-15

    申请号:US13315705

    申请日:2011-12-09

    IPC分类号: H01L29/20

    摘要: A semiconductor structure includes a III-nitride substrate having a top surface and an opposing bottom surface and a first III-nitride layer of a first conductivity type coupled to the top surface of the III-nitride substrate. The semiconductor structure also includes a second III-nitride layer of a second conductivity type coupled to the first III-nitride layer along a vertical direction and a third III-nitride layer of a third conductivity type coupled to the second III-nitride layer along the vertical direction. The semiconductor structure further includes a first trench extending through a portion of the third III-nitride layer to the first III-nitride layer, a second trench extending through another portion of the third III-nitride layer to the second III-nitride layer, and a first metal layer coupled to the second and the third III-nitride layers.

    摘要翻译: 半导体结构包括具有顶表面和相对底表面的III族氮化物衬底和与III族氮化物衬底的顶表面耦合的第一导电类型的第一III族氮化物层。 半导体结构还包括沿着垂直方向耦合到第一III族氮化物层的第二导电类型的第二III族氮化物层,以及沿着沿着垂直方向耦合到第二III族氮化物层的第三导电类型的第三III族氮化物层 垂直方向 半导体结构还包括延伸穿过第三III族氮化物层的一部分到第一III族氮化物层的第一沟槽,延伸穿过第三III族氮化物层的另一部分到第二III族氮化物层的第二沟槽,以及 耦合到第二和第三III族氮化物层的第一金属层。

    Optoelectronic devices including heterojunction and intermediate layer

    公开(公告)号:US09093591B2

    公开(公告)日:2015-07-28

    申请号:US13451455

    申请日:2012-04-19

    摘要: Embodiments generally relate to optoelectronic semiconductor devices such as solar cells. In one aspect, a device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to a back side of the device and is made of a different material and having a higher bandgap than the absorber layer. A heterojunction is formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction. An intermediate layer is located between the absorber layer and the emitter layer and provides the offset of the p-n junction from the heterojunction, and includes a graded layer and an ungraded back window layer.