公开(公告)号：US11658242B2

公开(公告)日：2023-05-23

申请号：US17524653

申请日：2021-11-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Haitao Liu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/04 ,  H01L27/108 ,  H01L29/45 ,  H01L29/08 ,  H01L29/10 ,  H01L29/267

CPC classification number: H01L29/7827 ,  H01L27/10808 ,  H01L29/04 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/267 ,  H01L29/456

Abstract: Some embodiments include an integrated assembly having a semiconductor material with a more-doped region adjacent to a less-doped region. A two-dimensional material is between the more-doped region and a portion of the less-doped region. Some embodiments include an integrated assembly which contains a semiconductor material, a metal-containing material over the semiconductor material, and a two-dimensional material between a portion of the semiconductor material and the metal-containing material. Some embodiments include a transistor having a first source/drain region, a second source/drain region, a channel region between the first and second source/drain regions, and a two-dimensional material between the channel region and the first source/drain region.

公开(公告)号：US20220068343A1

公开(公告)日：2022-03-03

申请号：US17501464

申请日：2021-10-14

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Durai Vishak Nirmal Ramaswamy ,  F. Daniel Gealy

IPC: G11C11/22 ,  H01L29/423 ,  H01L29/788 ,  H01L27/1159 ,  H01L29/78 ,  H01L29/66

Abstract: A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.

公开(公告)号：US20210313445A1

公开(公告)日：2021-10-07

申请号：US17348718

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L29/66 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/417 ,  H01L45/00 ,  H01L29/08 ,  H01L29/872 ,  H01L21/28 ,  H01L21/283 ,  H01L29/88

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

公开(公告)号：US20190280046A1

公开(公告)日：2019-09-12

申请号：US16423484

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: H01L27/24 ,  G11C11/39 ,  G11C11/56 ,  H01L45/00 ,  H01L29/66 ,  G11C13/00 ,  G11C11/34 ,  G11C5/02 ,  G11C11/402

Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

公开(公告)号：US10297612B2

公开(公告)日：2019-05-21

申请号：US16020712

申请日：2018-06-27

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L27/11585 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/24 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11578 ,  H01L27/11514 ,  G11C11/22

Abstract: A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.

公开(公告)号：US10134798B2

公开(公告)日：2018-11-20

申请号：US15284232

申请日：2016-10-03

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: H01L27/146 ,  H01L31/0352 ,  H01L31/11

Abstract: An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.

公开(公告)号：US20180308537A1

公开(公告)日：2018-10-25

申请号：US16011771

申请日：2018-06-19

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Durai Vishak Nirmal Ramaswamy ,  F. Daniel Gealy

IPC: G11C11/22 ,  H01L29/788 ,  H01L29/78 ,  H01L29/423 ,  G11C16/10 ,  H01L27/11568 ,  G11C16/04 ,  H01L29/792 ,  H01L27/1159

CPC classification number: G11C11/223 ,  G11C11/2275 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/11568 ,  H01L27/1159 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/788 ,  H01L29/7923

Abstract: A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.

公开(公告)号：US10062426B2

公开(公告)日：2018-08-28

申请号：US14260940

申请日：2014-04-24

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Durai Vishak Nirmal Ramaswamy ,  F. Daniel Gealy

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  G11C11/22 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11568 ,  H01L29/792 ,  H01L27/1159

CPC classification number: G11C11/223 ,  G11C11/2275 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/11568 ,  H01L27/1159 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/788 ,  H01L29/7923

Abstract: A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.

公开(公告)号：US09741737B1

公开(公告)日：2017-08-22

申请号：US15130803

申请日：2016-04-15

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L27/1157 ,  H01L28/00

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US20170117319A1

公开(公告)日：2017-04-27

申请号：US15284232

申请日：2016-10-03

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: H01L27/146 ,  H01L31/0352

CPC classification number: H01L27/14647 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/1461 ,  H01L27/14652 ,  H01L27/14689 ,  H01L31/0352 ,  H01L31/11

Abstract: An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.