公开(公告)号：US20200020407A1

公开(公告)日：2020-01-16

申请号：US16448502

申请日：2019-06-21

申请人： Micron Technology, Inc.

发明人： Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Gianni Stephen Alsasua ,  Ashutosh Malshe ,  Sampath Ratnam ,  Gary F. Besinga ,  Michael G. Miller

IPC分类号： G11C16/26

摘要： Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.

公开(公告)号：US10365854B1

公开(公告)日：2019-07-30

申请号：US15924951

申请日：2018-03-19

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Peter Sean Feeley ,  Ashutosh Malshe ,  Sampath Ratnam ,  Harish Singidi ,  Vamsi Pavan Rayaprolu

IPC分类号： G06F3/06

摘要： A variety of applications can include apparatus and/or methods that include tracking data temperatures of logical block addresses for a memory device by operating multiple accumulators by one or more data temperature analyzers to count host writes to ranges of logical block addresses. Data temperature for data written by a host is a measure of how frequently data at a logical block address is overwritten. In various embodiments, tracking can include staggering the start of counting by each of the multiple accumulators to provide subsequent binning of logical block addresses bands into temperature zones, which can achieve better data segregation. Data having a logical block address received from a host can be routed to a block associated with a temperature zone based on the binning provided by the staggered operation of the multiple accumulators by one or more data temperature analyzers. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US10354732B2

公开(公告)日：2019-07-16

申请号：US15690920

申请日：2017-08-30

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Sampath Ratnam ,  Preston Thomson ,  Harish Singidi ,  Jung Sheng Hoei ,  Peter Sean Feeley ,  Jianmin Huang

IPC分类号： G11C11/34 ,  G11C16/10 ,  G11C16/22

摘要： Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

公开(公告)号：US20190066739A1

公开(公告)日：2019-02-28

申请号：US15692407

申请日：2017-08-31

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Harish Singidi ,  Gianni Stephen Alsasua ,  Gary F. Besinga ,  Sampath Ratnam ,  Peter Sean Feeley

IPC分类号： G11C7/10 ,  G11C8/10

CPC分类号： G11C7/1006 ,  G11C8/10 ,  G11C29/023 ,  G11C29/028 ,  G11C2216/14 ,  G11C2216/22

摘要： A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US09183070B2

公开(公告)日：2015-11-10

申请号：US13949560

申请日：2013-07-24

申请人： Micron Technology, Inc.

发明人： Todd Marquart ,  Sampath Ratnam ,  Sean Eilert

IPC分类号： G06F11/07

CPC分类号： G06F11/0727 ,  G06F11/1048 ,  G06F2212/7204 ,  G06F2212/7206 ,  G06F2212/7211

摘要： In an embodiment, a block of memory cells is rested in response to the block of memory cells being deemed to fail. For some embodiments, a rested block may be selected for use in response to passing an operation. In other embodiments, a rested block may be rested again or may be permanently retired from further use in response to failing the operation.

摘要翻译： 在一个实施例中，响应于被认为失败的存储器单元的块，休息存储器单元块。 对于一些实施例，可以选择休息块以用于响应于通过操作。 在其他实施例中，可以再次休息一个休息块，或者可以响应于该操作失败而从进一步使用中永久退休。

公开(公告)号：US11610632B2

公开(公告)日：2023-03-21

申请号：US17331395

申请日：2021-05-26

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Sampath Ratnam ,  Preston Allen Thomson ,  Harish Reddy Singidi ,  Jung Sheng Hoei ,  Peter Sean Feeley ,  Jianmin Huang

IPC分类号： G11C16/10 ,  G11C16/22 ,  G11C16/04 ,  G11C16/34 ,  G11C16/28 ,  G11C29/02 ,  G11C16/20 ,  G11C11/56

摘要： Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

公开(公告)号：US20220392547A1

公开(公告)日：2022-12-08

申请号：US17820792

申请日：2022-08-18

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Karl Schuh ,  Mustafa N. Kaynak ,  Xiangang Luo ,  Shane Nowell ,  Devin Batutis ,  Sivagnanam Parthasarathy ,  Sampath Ratnam ,  Jiangang Wu ,  Peter Feeley

IPC分类号： G11C16/30 ,  G11C7/04 ,  G11C16/26 ,  G11C16/34 ,  G11C16/32 ,  G11C16/10

摘要： A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.

公开(公告)号：US11456037B2

公开(公告)日：2022-09-27

申请号：US17318603

申请日：2021-05-12

申请人： Micron Technology, Inc.

发明人： Harish Singidi ,  Kishore Kumar Muchherla ,  Gianni Stephen Alsasua ,  Ashutosh Malshe ,  Sampath Ratnam ,  Gary F. Besinga ,  Michael G. Miller

IPC分类号： G11C16/26 ,  G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/04

摘要： Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.

公开(公告)号：US20220188040A1

公开(公告)日：2022-06-16

申请号：US17685102

申请日：2022-03-02

申请人： Micron Technology, Inc.

发明人： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Peter Sean Feeley ,  Ashutosh Malshe ,  Renato Padilla, JR. ,  Kishore Kumar Muchherla ,  Sampath Ratnam

IPC分类号： G06F3/06 ,  G11C16/34

摘要： Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.

公开(公告)号：US11269553B2

公开(公告)日：2022-03-08

申请号：US16878304

申请日：2020-05-19

申请人： Micron Technology, Inc.

发明人： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Peter Sean Feeley ,  Ashutosh Malshe ,  Renato Padilla, Jr. ,  Kishore Kumar Muchherla ,  Sampath Ratnam

IPC分类号： G06F12/00 ,  G06F3/06 ,  G11C16/34

摘要： Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.