公开(公告)号：US09397166B2

公开(公告)日：2016-07-19

申请号：US13977394

申请日：2011-12-20

申请人： Van H. Le ,  Harold W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack Kavalieros ,  Niloy Mukherjee

发明人： Van H. Le ,  Harold W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack Kavalieros ,  Niloy Mukherjee

IPC分类号： H01L29/06 ,  H01L29/20 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  B82Y99/00

CPC分类号： H01L29/7848 ,  B82Y99/00 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  Y10S977/762

摘要： Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor. In embodiments of the invention, the transistor channel regions are comprised of germanium, silicon, a combination of germanium and silicon, or a combination of germanium, silicon, and tin and the source and drain regions are comprised of a doped III-V compound semiconductor material. Embodiments of the invention are useful in a variety of transistor structures, such as, for example, trigate, bigate, and single gate transistors and transistors having a channel region comprised of nanowires or nanoribbons.

摘要翻译： 本发明的实施例提供具有应变通道区域的晶体管结构。 通过源极和漏极区域中相对于晶体管的沟道区域的晶格失配产生应变。 在本发明的实施例中，晶体管沟道区由锗，硅，锗和硅的组合，或锗，硅和锡的组合组成，源极和漏极区由掺杂的III-V族化合物半导体 材料。 本发明的实施例可用于各种晶体管结构，例如具有由纳米线或纳米带构成的沟道区的触发，大电流和单栅极晶体管和晶体管。

公开(公告)号：US20130285017A1

公开(公告)日：2013-10-31

申请号：US13977394

申请日：2011-12-20

申请人： Van H. Le ,  Harold W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack Kavalieros ,  Niloy Mukherjee

发明人： Van H. Le ,  Harold W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack Kavalieros ,  Niloy Mukherjee

IPC分类号： H01L29/20 ,  H01L29/775

CPC分类号： H01L29/7848 ,  B82Y99/00 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  Y10S977/762

摘要： Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor. In embodiments of the invention, the transistor channel regions are comprised of germanium, silicon, a combination of germanium and silicon, or a combination of germanium, silicon, and tin and the source and drain regions are comprised of a doped III-V compound semiconductor material. Embodiments of the invention are useful in a variety of transistor structures, such as, for example, trigate, bigate, and single gate transistors and transistors having a channel region comprised of nanowires or nanoribbons.

摘要翻译： 本发明的实施例提供具有应变通道区域的晶体管结构。 通过源极和漏极区域中相对于晶体管的沟道区域的晶格失配产生应变。 在本发明的实施例中，晶体管沟道区由锗，硅，锗和硅的组合，或锗，硅和锡的组合组成，源极和漏极区由掺杂的III-V族化合物半导体 材料。 本发明的实施例可用于各种晶体管结构，例如具有由纳米线或纳米带构成的沟道区的触发，大电流和单栅极晶体管和晶体管。

公开(公告)号：US20180226509A1

公开(公告)日：2018-08-09

申请号：US15747925

申请日：2015-07-31

申请人： Elijah V. Karpov ,  Prashant Majhi ,  Roza Kotlyar ,  Niloy Mukherjee ,  Charles C. Kuo ,  Uday Shah ,  Ravi Pillarisetty ,  Robert S. Chau

发明人： Elijah V. Karpov ,  Prashant Majhi ,  Roza Kotlyar ,  Niloy Mukherjee ,  Charles C. Kuo ,  Uday Shah ,  Ravi Pillarisetty ,  Robert S. Chau

IPC分类号： H01L29/786 ,  H01L27/07 ,  H01L27/12 ,  H01L29/49 ,  H01L29/02

CPC分类号： H01L29/7869 ,  H01L27/0705 ,  H01L27/1225 ,  H01L27/2436 ,  H01L29/02 ,  H01L29/4908 ,  H01L29/78603 ,  H01L29/78642 ,  H01L45/04 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146

摘要： A microelectronic device having a functional metal oxide channel may be fabricated on a microelectronic substrate that can be utilized in very large scale integration, such as a silicon substrate, by forming a buffer transition layer between the microelectronic substrate and the functional metal oxide channel. In one embodiment, the microelectronic device may be a microelectronic transistor with a source structure and a drain structure formed on the buffer transition layer, wherein the source structure and the drain structure abut opposing sides of the functional metal oxide channel and a gate dielectric is disposed between a gate electrode and the functional metal oxide channel. In another embodiment, the microelectronic device may be a two-terminal microelectronic device.

公开(公告)号：US09711591B2

公开(公告)日：2017-07-18

申请号：US13997607

申请日：2011-12-28

申请人： Niloy Mukherjee ,  Matthew V. Metz ,  James M. Powers ,  Van H. Le ,  Benjamin Chu-Kung ,  Mark R. Lemay ,  Marko Radosavljevic ,  Niti Goel ,  Loren Chow ,  Peter G. Tolchinsky ,  Jack T. Kavalieros ,  Robert S. Chau

发明人： Niloy Mukherjee ,  Matthew V. Metz ,  James M. Powers ,  Van H. Le ,  Benjamin Chu-Kung ,  Mark R. Lemay ,  Marko Radosavljevic ,  Niti Goel ,  Loren Chow ,  Peter G. Tolchinsky ,  Jack T. Kavalieros ,  Robert S. Chau

IPC分类号： H01L21/02 ,  H01L29/06

CPC分类号： H01L29/06 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02587 ,  H01L21/0259 ,  H01L21/02617 ,  H01L21/02636 ,  H01L21/02658 ,  H01L21/02664

摘要： Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.

公开(公告)号：US09583574B2

公开(公告)日：2017-02-28

申请号：US13631514

申请日：2012-09-28

申请人： Sansaptak Dasgupta ,  Han Wui Then ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Robert S. Chau

发明人： Sansaptak Dasgupta ,  Han Wui Then ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Robert S. Chau

IPC分类号： H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778 ,  H01L29/423

CPC分类号： H01L29/7787 ,  H01L23/535 ,  H01L29/04 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66545

摘要： Embodiments include epitaxial semiconductor stacks for reduced defect densities in III-N device layers grown over non-III-N substrates, such as silicon substrates. In embodiments, a metamorphic buffer includes an AlxIn1-xN layer lattice matched to an overlying GaN device layers to reduce thermal mismatch induced defects. Such crystalline epitaxial semiconductor stacks may be device layers for HEMT or LED fabrication, for example. System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits may be provided on the semiconductor stacks in a first area of the silicon substrate while silicon-based CMOS circuitry is provided in a second area of the substrate.

摘要翻译： 实施例包括用于在诸如硅衬底的非III-N衬底上生长的III-N器件层中的缺陷密度降低的外延半导体堆叠。 在实施例中，变质缓冲器包括与上覆GaN器件层匹配的Al x In 1-x N层晶格以减少热失配引起的缺陷。 这种结晶外延半导体叠层可以是用于例如HEMT或LED制造的器件层。 使用基于能够实现高Ft的III族氮化物（III-N）的晶体管技术并且还具有足够高的击穿电压（BV）来实现高电压和/或高电平的片上系统（SoC）解决方案集成RFIC与PMIC 电源电路可以设置在硅衬底的第一区域中的半导体堆叠上，而硅基CMOS电路设置在衬底的第二区域中。

公开(公告)号：US20140326953A1

公开(公告)日：2014-11-06

申请号：US14334636

申请日：2014-07-17

申请人： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Willy Rachmady ,  Niloy Mukherjee ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Willy Rachmady ,  Niloy Mukherjee ,  Robert S. Chau

IPC分类号： H01L29/15 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/7784 ,  H01L29/151 ,  H01L29/155 ,  H01L29/201 ,  H01L29/205 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/7783 ,  H01L29/78

摘要： Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

摘要翻译： 公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。 这些技术可以用于例如形成与在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极，源极和漏极区的接触。 不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程，由本文所描述的技术提供的所得到的源极和漏极触点是自对准的，因为每个触点与栅电极对准并且被隔离 通过间隔材料。

公开(公告)号：US20140158976A1

公开(公告)日：2014-06-12

申请号：US13706473

申请日：2012-12-06

申请人： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Robert S. Chau

发明人： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Robert S. Chau

IPC分类号： H01L21/36 ,  H01L29/06

CPC分类号： H01L29/0684 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02642 ,  H01L21/02647 ,  H01L29/2003 ,  Y10S977/762

摘要： III-N semiconductor-on-silicon integrated circuit structures and techniques are disclosed. In some cases, the structure includes a first semiconductor layer formed on a nucleation layer, the first semiconductor layer including a 3-D GaN layer on the nucleation layer and having a plurality of 3-D semiconductor structures, and a 2-D GaN layer on the 3-D GaN layer. The structure also may include a second semiconductor layer formed on or within the first semiconductor layer, wherein the second semiconductor layer includes AlGaN on the 2-D GaN layer and a GaN layer on the AlGaN layer. Another structure includes a first semiconductor layer formed on a nucleation layer, the first semiconductor layer comprising a 2-D GaN layer on the nucleation layer, and a second semiconductor layer formed on or within the first semiconductor layer, wherein the second semiconductor layer includes AlGaN on the 2-D GaN layer and a GaN layer on the AlGaN layer.

摘要翻译： 公开了III-N半导体硅集成电路结构和技术。 在一些情况下，该结构包括在成核层上形成的第一半导体层，第一半导体层在成核层上包含3-D GaN层并具有多个3-D半导体结构，以及2-D ​​GaN层 在3-D GaN层上。 该结构还可以包括形成在第一半导体层上或第一半导体层内的第二半导体层，其中第二半导体层包括二维GaN层上的AlGaN和AlGaN层上的GaN层。 另一种结构包括形成在成核层上的第一半导体层，第一半导体层包括成核层上的2-D GaN层，以及形成在第一半导体层上或第一半导体层内的第二半导体层，其中第二半导体层包括AlGaN 在2-D GaN层和AlGaN层上的GaN层。

公开(公告)号：US20110147713A1

公开(公告)日：2011-06-23

申请号：US12646621

申请日：2009-12-23

申请人： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Willy Rachmady ,  Niloy Mukherjee ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Willy Rachmady ,  Niloy Mukherjee ,  Robert S. Chau

IPC分类号： H01L29/66 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7784 ,  H01L29/151 ,  H01L29/155 ,  H01L29/201 ,  H01L29/205 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/7783 ,  H01L29/78

摘要： Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

摘要翻译： 公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。 这些技术可以用于例如形成与在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极，源极和漏极区的接触。 不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程，由本文所描述的技术提供的所得到的源极和漏极触点是自对准的，因为每个触点与栅电极对准并且被隔离 通过间隔材料。

公开(公告)号：US20100035399A1

公开(公告)日：2010-02-11

申请号：US12228386

申请日：2008-08-11

申请人： Willy Rachmady ,  Jason W. Klaus ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Jack Kavalieros ,  Sean King

发明人： Willy Rachmady ,  Jason W. Klaus ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Jack Kavalieros ,  Sean King

IPC分类号： H01L21/336

CPC分类号： H01L29/41775 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/28556 ,  H01L29/41783

摘要： Embodiments of the present invention describe a method of fabricating low resistance contact layers on a semiconductor device. The semiconductor device comprises a substrate having source and drain regions. The substrate is alternatingly exposed to a first precursor and a second precursor to selectively deposit an amorphous semiconductor layer onto each of the source and drain regions. A metal layer is then deposited over the amorphous semiconductor layer on each of the source and drain regions. An annealing process is then performed on the substrate to allow the metal layer to react with amorphous semiconductor layer to form a low resistance contact layer on each of the source and drain regions. The low resistance contact layer on each of the source and drain regions can be formed as either a silicide layer or germanide layer depending on the type of precursors used.

摘要翻译： 本发明的实施例描述了在半导体器件上制造低电阻接触层的方法。 半导体器件包括具有源区和漏区的衬底。 将基板交替地暴露于第一前体和第二前体，以将非晶半导体层选择性地沉积到源极和漏极区域中的每一个上。 然后在每个源极和漏极区域上的非晶半导体层上沉积金属层。 然后在衬底上进行退火处理，以允许金属层与非晶半导体层反应，以在源极和漏极区域中的每一个上形成低电阻接触层。 根据所使用的前体的类型，源极和漏极区域中的每一个上的低电阻接触层可以形成为硅化物层或锗化物层。

公开(公告)号：US09356099B2

公开(公告)日：2016-05-31

申请号：US14334636

申请日：2014-07-17

申请人： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Willy Rachmady ,  Niloy Mukherjee ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Willy Rachmady ,  Niloy Mukherjee ,  Robert S. Chau

IPC分类号： H01L29/15 ,  H01L29/41 ,  H01L29/78 ,  H01L29/66 ,  H01L29/778 ,  H01L29/775 ,  H01L29/417 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L29/7784 ,  H01L29/151 ,  H01L29/155 ,  H01L29/201 ,  H01L29/205 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/7783 ,  H01L29/78

摘要： Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.