公开(公告)号：US20170077918A1

公开(公告)日：2017-03-16

申请号：US14855238

申请日：2015-09-15

Applicant: QUALCOMM Incorporated

Inventor： Neha Agrawal ,  Sajin Mohamad ,  Chulkyu Lee

IPC: H03K7/06 ,  H03K3/037 ,  H03K19/21

CPC classification number: H03K7/06 ,  G06F1/08 ,  H03K3/037 ,  H03K19/21 ,  H03K21/00 ,  H03K21/026 ,  H03K21/10 ,  H03K23/00 ,  H03K23/64

Abstract: Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.

Abstract translation: 通过可编程分频比对输入时钟信号进行分频的系统和方法可以产生输出时钟信号，输出时钟信号与输入时钟信号的延迟无关于分频比的值，输出时钟信号的占空比为50 ％独立于分频比的值。 示例性可编程时钟分频器包括模N计数器，其产生计数分频比的计数信号和产生公共半速率时钟信号的半速率时钟信号发生器，偶数半速率时钟信号和奇数 半速率时钟信号以输出时钟信号的一半速率切换。 公共半速时钟信号，偶数半速率时钟信号和奇数半速率时钟信号被组合以产生输出时钟信号。

公开(公告)号：US20170060218A1

公开(公告)日：2017-03-02

申请号：US15302767

申请日：2014-05-21

Applicant: Wenjen SU ,  Le ZHANG ,  Chulkyu LEE ,  QUALCOMM Incorporated

Inventor： Le Zhang ,  Wenjun Su ,  Chulkyu Lee

IPC: G06F1/32 ,  G06F13/42 ,  G06F1/08 ,  G06F13/40 ,  H03M9/00 ,  G11C19/28

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F13/4022 ,  G06F13/4282 ,  G11C19/28 ,  H03M9/00 ,  Y02D10/14 ,  Y02D10/151

Abstract: Serializers and deserializers for odd ratio parallel data buses are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits work with a half-rate clock to provide a serial data stream at a full clock rate. By providing a half-rate clock, power and area are conserved on the integrated circuit incorporating the serializer. Additionally, by providing a 7:1 serializer, the bus is now compatible with the MIPI C-PHY standard.

Abstract translation: 公开了用于奇数比并行数据总线的串行器和解串器。 在一个实施例中，以奇数个并行数据位操作的串行器和解串行器与半速率时钟一起工作，以全时钟速率提供串行数据流。 通过提供半速率时钟，集成了串行器的集成电路的功率和面积是保守的。 此外，通过提供7：1串行器，该总线现在与MIPI C-PHY标准兼容。

公开(公告)号：US20170039163A1

公开(公告)日：2017-02-09

申请号：US15332756

申请日：2016-10-24

Applicant: QUALCOMM Incorporated

Inventor： Dhaval Sejpal ,  Shih-Wei Chou ,  Chulkyu Lee ,  Ohjoon Kwon ,  George Alan Wiley

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F13/4278 ,  H04L25/4917

Abstract: Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. One method includes providing a plurality of launch clock signals, including launch clock signals having a different phase shifts, determining a type of transition in signaling state that will occur on each wire of the 3-wire interface at a boundary between two consecutively transmitted symbols, and selecting one of the plurality of launch clock signals to initiate the transition of signaling state on each wire of the 3-phase interface. Selecting one of the plurality of launch clock signals may include selecting a first launch clock signal when the transition in signaling state terminates at an undriven state, and selecting a second launch clock signal when the transition in signaling state begins at an undriven state. An edge in the first launch clock signal may occur before a corresponding edge in the second launch clock signal.

Abstract translation: 公开了用于在多线接口上的传输中的错误检测的装置，系统和方法。 一种方法包括提供多个发射时钟信号，包括具有不同相移的发射时钟信号，确定将在两条连续发射的符号之间的边界处在3线接口的每条线路上发生的信令状态的转换类型， 以及选择所述多个发射时钟信号之一以启动所述三相接口的每条线路上的信令状态的转换。 选择多个发射时钟信号中的一个可以包括当信令状态的转换在未驱动状态下终止时选择第一发射时钟信号，以及当信令状态的转变在未驱动状态开始时选择第二发射时钟信号。 第一个启动时钟信号中的边沿可能发生在第二个启动时钟信号的相应边沿之前。

公开(公告)号：US20160373141A1

公开(公告)日：2016-12-22

申请号：US15172913

申请日：2016-06-03

Applicant: QUALCOMM Incorporated

Inventor： Shih-Wei Chou ,  Chulkyu Lee ,  Dhaval Sejpal

IPC: H04B1/04 ,  H04B3/52

CPC classification number: H04B1/04 ,  G06F13/4072 ,  H04B3/52 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/493

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level. The dedicated transistor is activated based on a voltage level for driving a second terminal of the three terminals and a voltage level for driving a third terminal of the three terminals.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 当传输线否则将被驱动时，传输线选择性地终止在N相极性编码的发射机中。 数据被映射到要在多根线上传输的符号序列。 符号序列被编码为三个信号。 可以驱动多个端子的第一端子，使得晶体管被激活以将第一端子耦合到第一和第二电压电平。 第一端子可以进一步被驱动，使得专用晶体管被激活以将第一端子耦合到中间电压电平。 专用晶体管基于用于驱动三个端子的第二端子的电压电平和用于驱动三个端子的第三端子的电压电平而被激活。

公开(公告)号：US09521058B2

公开(公告)日：2016-12-13

申请号：US15097027

申请日：2016-04-12

Applicant: QUALCOMM Incorporated

Inventor： Shree Krishna Pandey ,  Arun Chandra Kundu ,  George Alan Wiley ,  Chulkyu Lee

IPC: H04L25/02 ,  H04L12/26 ,  H04L7/00 ,  H04B3/00 ,  H04B3/462 ,  H04B3/54

CPC classification number: H04L43/087 ,  G06F13/40 ,  H04B3/00 ,  H04B3/462 ,  H04B3/542 ,  H04L7/0041 ,  H04L25/0264 ,  H04L25/14

Abstract: In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.

Abstract translation: 在包括至少三条线的多线通道中，多线通道的每条独特的线对具有大致相同的信号传播时间。 以这种方式，可以在用于信令的多线信道中减轻抖动，其中对于给定的数据传输，差分信号在特定的一对导线上传输，并且每隔一个线路浮动。 在一些实现中，信号传播时间的匹配涉及为至少一条电线提供额外的延迟。 使用无源信号延迟技术和/或有源信号延迟技术来提供额外的延迟。

公开(公告)号：US09369237B2

公开(公告)日：2016-06-14

申请号：US14453287

申请日：2014-08-06

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley ,  Chulkyu Lee

IPC: H04L1/00 ,  H04L12/26 ,  H04L25/02 ,  H04L25/14 ,  H04L25/49

CPC classification number: H04L1/0056 ,  H04L1/0014 ,  H04L25/0272 ,  H04L25/14 ,  H04L25/49 ,  H04L43/0811

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. The apparatus may determine whether a run-length violation will occur or is likely to occur if a first sequence of symbols provided by a mapper of an M-Wire N-Phase encoder is transmitted on a plurality of wires. A second sequence of symbols may be substituted for the first sequence of symbols. The second sequence of symbols may comprise a surplus sequence of symbols that is not used for mapping data in the mapper.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 如果由M-Wire N相编码器的映射器提供的第一符号序列在多个导线上传输，则装置可以确定是否会发生游程长度违规或可能发生游程长度违例。 符号的第二序列可以代替第一符号序列。 第二符号序列可以包括不用于映射器中的数据的多余符号序列。

公开(公告)号：US09363071B2

公开(公告)日：2016-06-07

申请号：US14199322

申请日：2014-03-06

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  Chulkyu Lee ,  George Alan Wiley ,  Joseph Cheung

IPC: H04B3/00 ,  H04L7/033 ,  H04L7/027 ,  H04L7/00 ,  H04L25/49 ,  H04L25/493 ,  H03K5/1252 ,  H03K5/1534 ,  H04L25/14 ,  H04L25/02

CPC classification number: H04L7/033 ,  H03K5/1252 ,  H03K5/1534 ,  H04L7/0066 ,  H04L7/027 ,  H04L25/0272 ,  H04L25/14 ,  H04L25/49 ,  H04L25/4906 ,  H04L25/493

Abstract: A clock recovery circuit is provided comprising a receiver circuit and a clock extraction circuit. The receiver circuit may be adapted to decode a differentially encoded signal on a plurality of data lines, where at least one data symbol is differentially encoded in state transitions of the differentially encoded signal. The clock extraction circuit may be adapted to obtain a clock signal from state transition signals derived from the state transitions.

Abstract translation: 提供了一种包括接收机电路和时钟提取电路的时钟恢复电路。 接收器电路可以适于对多条数据线上的差分编码信号进行解码，其中至少一个数据符号在差分编码信号的状态转换中进行差分编码。 时钟提取电路可以适于从状态转换导出的状态转变信号获得时钟信号。

公开(公告)号：US20150381340A1

公开(公告)日：2015-12-31

申请号：US14315142

申请日：2014-06-25

Applicant: QUALCOMM Incorporated

Inventor： Shree Krishna Pandey ,  Arun Chandra Kundu ,  George Alan Wiley ,  Chulkyu Lee

IPC: H04L7/00 ,  H04B3/462 ,  H04B3/54

CPC classification number: H04L7/0041 ,  H04B3/00 ,  H04B3/462 ,  H04B3/542 ,  H04L25/0264

Abstract: In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.

Abstract translation: 在包括至少三条电线的多线通道中，多线通道的每条唯一的线对具有大致相同的信号传播时间。 以这种方式，可以在用于信令的多线信道中减轻抖动，其中对于给定的数据传输，差分信号在特定的一对导线上传输，并且每隔一个线路浮动。 在一些实现中，信号传播时间的匹配涉及为至少一条电线提供额外的延迟。 使用无源信号延迟技术和/或有源信号延迟技术来提供额外的延迟。

公开(公告)号：US09137008B2

公开(公告)日：2015-09-15

申请号：US14336572

申请日：2014-07-21

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley ,  Chulkyu Lee

IPC: H04L25/02 ,  H04L7/033 ,  H04B3/02 ,  G06F13/42

CPC classification number: H04L7/033 ,  G06F13/4295 ,  H04B3/02 ,  H04L7/0004 ,  H04L7/0337 ,  H04L25/0272 ,  H04L25/0292 ,  Y02D10/14 ,  Y02D10/151

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. A clock recovery circuit may be calibrated based on state transitions in a preamble transmitted on two or more connectors. A calibration method is described. The method includes detecting a plurality of transitions in a preamble of a multiphase signal and calibrating a delay element to provide a delay that matches a clocking period of the multiphase signal. Each transition may be detected by only one of a plurality of detectors. The delay element may be calibrated based on time intervals between detections of successive ones of the plurality of transitions.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 信息以N相极性编码符号发送。 时钟恢复电路可以基于在两个或更多个连接器上发送的前置码中的状态转换来校准。 描述校准方法。 该方法包括检测多相信号的前导码中的多个转换并校准延迟元件以提供与多相信号的计时周期匹配的延迟。 每个转换可以仅由多个检测器中的一个检测。 延迟元件可以基于多个转换中的连续检测之间的时间间隔进行校准。

公开(公告)号：US09130735B2

公开(公告)日：2015-09-08

申请号：US14336977

申请日：2014-07-21

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu Lee ,  George Alan Wiley ,  Richard Dominic Wietfeldt

IPC: H04B3/50 ,  H04L7/00 ,  H04L7/033 ,  G06F13/42

CPC classification number: H04L7/033 ,  G06F13/4295 ,  H04B3/50 ,  H04L7/00 ,  H04L7/0037 ,  H04L7/0041

Abstract: Systems and methods for multi-phase signaling are described herein. In one embodiment, a method for receiving data comprises receiving a sequence of symbols from a plurality of conductors, and generating a clock signal by detecting transitions in the received sequence of symbols. The method also comprises delaying the received sequence of symbols, and capturing one or more symbols in the delayed sequence of symbols using the clock signal, wherein a previous symbol in the delayed sequence of symbols is captured using a clock pulse in the clock signal generated based on a detected transition to a current symbol in the received sequence of symbols.

Abstract translation: 本文描述了用于多相信令的系统和方法。 在一个实施例中，一种用于接收数据的方法包括从多个导体接收符号序列，以及通过检测所接收的符号序列中的转变来产生时钟信号。 该方法还包括延迟接收到的符号序列，并使用时钟信号捕获延迟符号序列中的一个或多个符号，其中使用基于时钟信号生成的时钟信号中的时钟脉冲来捕获延迟符号序列中的先前符号 在所接收的符号序列中检测到到当前符号的转换。