公开(公告)号：US20170139469A1

公开(公告)日：2017-05-18

申请号：US14940065

申请日：2015-11-12

Applicant: QUALCOMM INCORPORATED

Inventor： RICHARD STEWART ,  Dexter Tamio Chun ,  Alain Artieri

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3287 ,  Y02D10/172 ,  Y02D50/20

Abstract: Components of a portable computing device produce power supply voltage requests indicating requested power levels. In response to the power supply voltage requests, power multiplexers associated with the components select and couple corresponding voltage rails associated with two or more fixed-voltage power supplies to the requesting components. Power supplies may be activated and deactivated on an as-requested basis.

公开(公告)号：US09639128B2

公开(公告)日：2017-05-02

申请号：US14818180

申请日：2015-08-04

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter Tamio Chun

IPC: G06F1/20 ,  G06F3/06

CPC classification number: G06F1/206 ,  G06F1/203 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0673 ,  G11C7/04

Abstract: Systems, methods, and computer programs, embodied in or as a memory management module, are disclosed for thermally controlling memory to increase its performance. One exemplary embodiment includes a memory, one or more processors, and a thermoelectric cooling device. The one or more processors access the memory via a memory controller electrically coupled to the memory. The thermoelectric cooling device is configured to thermally control the memory in response to a predicted change in temperature of the memory.

公开(公告)号：US09633698B2

公开(公告)日：2017-04-25

申请号：US14280313

申请日：2014-05-16

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Vaishnav Srinivas ,  David Ian West ,  Deepti Vijayalakshmi Sriramagiri ,  Jungwon Suh ,  Jason Thurston

IPC: G06F11/00 ,  G11C5/14 ,  G06F11/07 ,  G06F11/10 ,  G01R31/317

CPC classification number: G11C5/147 ,  G01R31/31709 ,  G01R31/3171 ,  G06F11/076 ,  G06F11/1004

Abstract: Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data.

公开(公告)号：US09547361B2

公开(公告)日：2017-01-17

申请号：US14700017

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Ali Taha ,  Dexter Tamio Chun

IPC: G06F1/32 ,  G11C11/40 ,  G11C14/00 ,  G11C11/406

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F2212/1028 ,  G06F2212/205 ,  G11C11/406 ,  G11C14/0009 ,  G11C14/0054 ,  Y02D10/13 ,  Y02D10/14

Abstract: Methods and apparatuses for memory power reduction are provided. The apparatus determines whether to store data into a DRAM or an NVRAM during an idle state of a processor based on power consumption by the DRAM in association with refreshing the data in the DRAM and use of the data stored in the DRAM by the processor, based on power consumption by the NVRAM in association with use of the data stored in the NVRAM by the processor, and based on a duty cycle associated with current drawn in a first power state and a second power state in association with the data. The NVRAM is a type of non-volatile random-access memory other than flash memory. The processor stores the data into one of the DRAM or the NVRAM based on the determination whether to store the data in the DRAM or the NVRAM.

Abstract translation: 提供了用于存储器功率降低的方法和装置。 该设备基于DRAM的功耗与DRAM中的数据相关联以及处理器中存储在DRAM中的数据的使用，确定在处理器的空闲状态期间是否将数据存储到DRAM或NVRAM中 关于由处理器使用存储在NVRAM中的数据以及与数据相关联的与第一功率状态和第二功率状态相关联的电流相关联的占空比，由NVRAM产生的功率消耗。 NVRAM是除闪存之外的一种非易失性随机存取存储器。 基于确定是否将数据存储在DRAM或NVRAM中，处理器将数据存储到DRAM或NVRAM之一中。

公开(公告)号：US20160307620A1

公开(公告)日：2016-10-20

申请号：US14690204

申请日：2015-04-17

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Jung Pill Kim ,  Yanru Li

IPC: G11C11/406 ,  G11C29/42 ,  G11C29/36 ,  G11C11/4096

CPC classification number: G11C11/40626 ,  G11C7/1006 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C29/36 ,  G11C29/42 ,  G11C29/50016 ,  G11C2207/2245 ,  G11C2211/4062

Abstract: A system and method of refreshing dynamic random access memory (DRAM) are disclosed. A device includes a DRAM, a bus, and a system-on-chip (SOC) coupled via the bus to the DRAM. The SOC is configured to refresh the DRAM at a particular refresh rate based on a temperature of the DRAM and based on calibration data determined based on one or more calibration tests performed while the SOC is coupled to the DRAM.

Abstract translation: 公开了一种刷新动态随机存取存储器（DRAM）的系统和方法。 一种器件包括通过总线耦合到DRAM的DRAM，总线和片上系统（SOC）。 SOC被配置为基于DRAM的温度以基于在SOC耦合到DRAM时执行的一个或多个校准测试确定的校准数据以特定刷新速率刷新DRAM。

公开(公告)号：US09461626B2

公开(公告)日：2016-10-04

申请号：US14330464

申请日：2014-07-14

Applicant: QUALCOMM Incorporated

Inventor： Hee Jun Park ,  Dexter Tamio Chun

IPC: H03K3/012 ,  H03K3/011 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/4093

CPC classification number: H03K3/012 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4074 ,  G11C11/4093 ,  H03K3/011

Abstract: Techniques for adjusting swing voltage for an I/O interface signal are described herein. In one embodiment, a device comprises an input/output (I/O) interface, and an I/O voltage controller. The I/O voltage controller is configured to determine a frequency or temperature of the I/O interface, and to adjust a swing voltage of the I/O interface based at least in part upon the determined frequency or temperature.

Abstract translation: 本文描述了用于调整I / O接口信号的摆动电压的技术。 在一个实施例中，设备包括输入/​​输出（I / O）接口和I / O电压控制器。 I / O电压控制器被配置为确定I / O接口的频率或温度，并且至少部分地基于所确定的频率或温度来调整I / O接口的摆幅电压。

公开(公告)号：US20160093345A1

公开(公告)日：2016-03-31

申请号：US14497902

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Michael Drop ,  Raghu Sankuratri

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G06F13/1689

Abstract: A method includes detecting, at a controller, a rate-of-change between first data traffic to be sent to a dynamic random access memory (DRAM) at a first time and second data traffic to be sent to the DRAM at a second time. The method also includes adjusting a data rate of the second data traffic in response to a determination that the rate-of-change satisfies a threshold.

Abstract translation: 一种方法包括在控制器处检测要发送到第一时间的动态随机存取存储器（DRAM）的第一数据业务和第二时间发送到DRAM的第二数据业务之间的变化率。 该方法还包括响应于变化率满足阈值的确定来调整第二数据业务的数据速率。

公开(公告)号：US09087765B2

公开(公告)日：2015-07-21

申请号：US13839816

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Jungwon Suh ,  Urmi Ray ,  Shiqun Gu

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/16 ,  H01L23/14 ,  H01L23/31 ,  H01L23/373 ,  H01L23/15

CPC classification number: H01L23/16 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3737 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/13 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/11

Abstract: An integrated circuit package is disclosed that includes a first-pitch die and a second-pitch die. The second-pitch die interconnects to the second-pitch substrate through second-pitch substrates. The first-pitch die interconnects through first-pitch interconnects to an interposer adapter. The pitch of the first-pitch interconnects is too fine for the second-pitch substrate. But the interposer adapter interconnects through second-pitch interconnects to the second-pitch substrate and includes through substrate vias so that I/O signaling between the first-pitch die and the second-pitch die can be conducted through the second-pitch substrate and through the through substrate vias in the interposer adapter.

Abstract translation: 公开了一种集成电路封装，其包括第一间距管芯和第二间距管芯。 第二间距模具通过第二间距基板与第二间距基板相互连接。 第一间距模具通过第一间距互连件互连到插入器适配器。 第一节距互连的间距对于第二间距衬底来说太细了。 但是插入器适配器通过第二间距互连件连接到第二间距衬底并且包括通过衬底通孔，使得第一间距管芯和第二间距管芯之间的I / O信号可以通过第二间距衬底并且通过 贯穿衬底通孔插入插座适配器中。

公开(公告)号：US20250111885A1

公开(公告)日：2025-04-03

申请号：US18978617

申请日：2024-12-12

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Anand Srinivasan ,  Olivier Alavoine ,  Laurent Rene Moll

IPC: G11C29/42 ,  G11C7/10 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44

Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

公开(公告)号：US12230347B2

公开(公告)日：2025-02-18

申请号：US18322997

申请日：2023-05-24

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Anand Srinivasan ,  Olivier Alavoine ,  Laurent Rene Moll

IPC: G11C29/42 ,  G11C7/10 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44

Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.