公开(公告)号：US09659820B2

公开(公告)日：2017-05-23

申请号：US15143969

申请日：2016-05-02

Applicant: International Business Machines Corporation ,  STMICROELECTRONICS, INC.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise ,  Akil K. Sutton ,  Terry Allen Spooner ,  Nicole A. Saulnier

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

公开(公告)号：US09658523B2

公开(公告)日：2017-05-23

申请号：US14231448

申请日：2014-03-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise ,  Terry Spooner ,  Nicole A. Saulnier

IPC: G03F1/36 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/027 ,  H01L21/311

CPC classification number: G03F1/36 ,  G03F1/00 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wavy line interconnect structure that accommodates small metal lines and large vias is disclosed. A lithography mask design used to pattern metal line trenches uses optical proximity correction (OPC) techniques to approximate wavy lines using rectangular opaque features. The large vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. Instead, a sacrificial layer allows etching of an underlying thick dielectric block, while protecting narrow features of the trenches that correspond to the metal line interconnects. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By lifting the shrink constraint for vias, thereby allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

公开(公告)号：US20170110317A1

公开(公告)日：2017-04-20

申请号：US15391135

申请日：2016-12-27

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/02 ,  B08B3/08 ,  B08B3/12 ,  H01L21/67

CPC classification number: H01L21/02057 ,  B08B3/08 ,  B08B3/12 ,  H01L21/67028 ,  H01L21/67046

Abstract: A brush-cleaning apparatus is disclosed for use in cleaning a semiconductor wafer after polishing. Embodiments of the brush-cleaning apparatus implemented with a multi-branch chemical dispensing unit are applied beneficially to clean semiconductor wafers, post-polish, using a hybrid cleaning method. An exemplary hybrid cleaning method employs a two-chemical sequence in which first and second chemical treatment modules are separate from one another, and are followed by a pH-neutralizing—rinse that occurs in a treatment module separate from the first and second chemical treatment modules. Implementation of such hybrid methods is facilitated by the multi-branch chemical dispensing unit, which provides separate chemical lines to different chemical treatment modules, and dispenses chemical to at least four different areas of each wafer during single-wafer processing in an upright orientation. The multi-branch chemical dispensing unit provides a flexible, modular building block for constructing various equipment configurations that use multiple chemical treatments and/or pH neutralization steps.

公开(公告)号：US09405065B2

公开(公告)日：2016-08-02

申请号：US14045640

申请日：2013-10-03

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L23/48 ,  G02B6/122 ,  H01L23/522 ,  H01L23/532 ,  H01L21/66

CPC classification number: G02B6/132 ,  G02B6/122 ,  G02B6/1225 ,  G02B6/13 ,  G02B6/136 ,  G02B2006/121 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/76883 ,  H01L22/12 ,  H01L22/14 ,  H01L23/522 ,  H01L23/53209 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission.

Abstract translation: 本文中呈现的一系列处理步骤用于仅使用一个光刻步骤将光信号路径嵌入纳米线阵列内。 使用所公开的技术，在形成光学特征的同时不需要屏蔽电气特征，反之亦然。 相反，可以在相同的掩蔽周期中基本上同时地创建光学和电信号路径。 这可以通过各个特征的宽度的差异来实现，光信号路径比电的宽度明显更宽。 使用镶嵌工艺，不同宽度的结构镀金属，其过度填充狭窄的沟槽并且填充宽的沟槽。 然后可以将光学包覆材料沉积到沟槽中，以便围绕用于光透射的光学芯。

公开(公告)号：US09337252B1

公开(公告)日：2016-05-10

申请号：US14982061

申请日：2015-12-29

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L21/20 ,  H01L49/02 ,  H01L21/768 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0676 ,  H01L27/0682 ,  H01L27/0802 ,  H01L28/20 ,  H01L28/24 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.

Abstract translation: 制造半导体器件的方法可以包括在半导体衬底上形成第一电介质层，在第一电介质层中形成第一沟槽，用导电材料填充第一沟槽，去除导电材料的上部以限定下部 导电构件，其上方具有凹部，在凹部中形成填充介电材料以限定第二沟槽。 该方法还可以包括用导电材料填充第二沟槽以限定上导电构件，在第一电介质层和上导电构件上形成第二电介质层，形成通过第二电介质层和下面的填充介电材料的第一通孔， 下导电构件，并且通过第二电介质层形成到上导电构件的第二通孔。

公开(公告)号：US09324660B2

公开(公告)日：2016-04-26

申请号：US14038574

申请日：2013-09-26

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Walter Kleemeier ,  Paul Ferreira ,  Ronald K. Sampson

IPC: H01L23/544 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/544 ,  H01L22/14 ,  H01L22/22 ,  H01L22/34 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

公开(公告)号：US20160111521A1

公开(公告)日：2016-04-21

申请号：US14982316

申请日：2015-12-29

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/66492 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823842 ,  H01L22/12 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/413 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66431 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7781 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

Abstract translation: 将金属量子点（例如，溴化银（AgBr）膜）引入MOSFET的源极和漏极区域可以通过调整阈值电压来帮助控制晶体管的性能。 如果溴化银膜富含溴原子，则沉积阴离子量子点，改变AgBr能隙以增加Vt，如果溴化银膜富含银原子，则沉积阳离子量子点，AgBr 能量间隙被改变以便降低Vt，不同尺寸的中性量子点的原子层沉积（ALD）也变化Vt。在膜沉积期间使用质谱仪可以帮助改变量子点膜的组成。 金属量子点可以结合到离子掺杂的源极和漏极区域中。 或者，金属量子点可以并入外延掺杂的源区和漏区。

公开(公告)号：US20160064326A1

公开(公告)日：2016-03-03

申请号：US14937812

申请日：2015-11-10

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Yiheng Xu ,  Lawrence A. Clevenger ,  Carl Radens ,  Edem Wornyo

IPC: H01L23/525 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01F17/0006 ,  H01F17/02 ,  H01F2017/0073 ,  H01L23/522 ,  H01L23/5227 ,  H01L23/5252 ,  H01L28/10 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.

公开(公告)号：US20150318285A1

公开(公告)日：2015-11-05

申请号：US14266384

申请日：2014-04-30

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L27/108 ,  H01L21/02 ,  H01L49/02

CPC classification number: H01L28/56 ,  H01L21/02197 ,  H01L21/28291 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65

Abstract: An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.

Abstract translation: 公开了一种用于集成电路中的耦合晶体管的互连结构，包括其中呈现负电容的铁电电容与介质电容器串联耦合的各种配置。 在一个实施例中，负电容器包括电介质/铁电双层。 当负电容器与传统介质电容器串联电耦合时，串联组合的行为就像一个稳定的铁电电容器，其整体电容可以通过实验测量并调谐到所需的值。 在理论上，介电电容器和负电容串联的铁电电容器的复合电容在理论上是无限的，并且在实践中非常大。 可以使用微电子互连结构内的正和负电容器的串联组合来制造高容量DRAM存储器单元。

公开(公告)号：US20150279695A1

公开(公告)日：2015-10-01

申请号：US14231533

申请日：2014-03-31

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/321 ,  H01L21/67 ,  H01L21/306

CPC classification number: H01L21/3212 ,  B24B37/005 ,  H01L21/02074 ,  H01L21/6704 ,  H01L21/67207 ,  H01L21/67219 ,  H01L21/67253 ,  H01L21/67706 ,  H01L22/14 ,  H01L22/20

Abstract: CMP selectivity, removal rate, and uniformity are controlled both locally and globally by altering electric charge at the wafer surface. Surface charge characterization is performed by an on-board metrology module. Based on a charge profile map, the wafer can be treated in an immersion bath to impart a more positive or negative charge overall, or to neutralize the entire wafer before the CMP operation is performed. If charge hot spots are detected on the wafer, a charge pencil can be used to neutralize localized areas. One type of charge pencil bears a tapered porous polymer tip that is placed in close proximity to the wafer surface. Films present on the wafer absorb ions from, or surrender ions to, the charge pencil tip, by electrostatic forces. The charge pencil can be incorporated into a CMP system to provide an in-situ treatment prior to the planarization step or the slurry removal step.

Abstract translation: 通过改变晶片表面的电荷，局部和全局地控制CMP选择性，去除速率和均匀性。 表面电荷表征由机载测量模块执行。 基于电荷分布图，晶片可以在浸没浴中进行处理以赋予整体更多的正电荷或负电荷，或者在执行CMP操作之前中和整个晶片。 如果在晶片上检测到充电热点，则可以使用充电笔来中和局部区域。 一种类型的充电笔带有一个倾斜的多孔聚合物顶端，其被放置在紧靠晶片表面的位置。 存在于晶片上的膜通过静电力吸收离子或将离子放置到电荷铅笔尖。 电荷铅笔可以结合到CMP系统中以在平坦化步骤或浆料去除步骤之前提供原位处理。