公开(公告)号：US06570419B2

公开(公告)日：2003-05-27

申请号：US09840191

申请日：2001-04-24

申请人： Satoru Hanzawa ,  Takeshi Sakata ,  Katsutaka Kimura

发明人： Satoru Hanzawa ,  Takeshi Sakata ,  Katsutaka Kimura

IPC分类号： H03L700

CPC分类号： H03K5/135 ,  H03K5/133 ,  H03L7/0814 ,  H03L7/0818 ,  H04L7/0008

摘要： A clock recovery circuit is provided for use in a memory with a clock synchronized interface, wherein an external clock is temporarily intercepted to shorten lock-in time when an internal clock is to be generated from the external clock. The clock recovery circuit includes a delay circuit array, receiving the external clock, for generating reference clocks, a control circuit comparing phases of the external clock and of the reference clocks and detecting the number of delay stages required for locking in, and a latching circuit for holding the number of delay stages required for locking in. Once synchronism is detected, the generation of internal clock can be resumed in a short period of time even if the supply of the external clock is temporarily suspended.

摘要翻译： 提供了一种用于具有时钟同步接口的存储器中的时钟恢复电路，其中当从外部时钟产生内部时钟时，临时截取外部时钟以缩短锁定时间。 时钟恢复电路包括：延迟电路阵列，接收用于产生参考时钟的外部时钟;控制电路，比较外部时钟和参考时钟的相位，并检测锁定所需的延迟级数;锁存电路 用于保持锁定所需的延迟级数。一旦检测到同步，即使暂时停止外部时钟的供给，也可以在短时间内恢复内部时钟的产生。

公开(公告)号：US06549484B2

公开(公告)日：2003-04-15

申请号：US09964669

申请日：2001-09-28

申请人： Sadayuki Morita ,  Takeshi Sakata ,  Satoru Hanzawa ,  Takahiro Sonoda ,  Haruko Tadokoro ,  Hiroshi Ichikawa ,  Osamu Nagashima

发明人： Sadayuki Morita ,  Takeshi Sakata ,  Satoru Hanzawa ,  Takahiro Sonoda ,  Haruko Tadokoro ,  Hiroshi Ichikawa ,  Osamu Nagashima

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.

公开(公告)号：US06489824B2

公开(公告)日：2002-12-03

申请号：US09935717

申请日：2001-08-24

申请人： Masayuki Miyazaki ,  Koichiro Ishibashi ,  Takeshi Sakata ,  Satoru Hanzawa ,  Hiroyuki Mizuno ,  Kiyoshi Hasegawa ,  Masaru Kokubo ,  Hirokazu Aoki

发明人： Masayuki Miyazaki ,  Koichiro Ishibashi ,  Takeshi Sakata ,  Satoru Hanzawa ,  Hiroyuki Mizuno ,  Kiyoshi Hasegawa ,  Masaru Kokubo ,  Hirokazu Aoki

IPC分类号： H03L706

CPC分类号： H04L7/0008 ,  G06F1/10 ,  H03K5/135 ,  H04L7/0037

摘要： A timing-control circuit device, which uses a synchronous mirror delay circuit, for keeping the synchronization between clock signals in phase even at a load change. A reference clock signal (clkin 11) is entered to a timing-control circuit (SMDF 14) and used to generate an internal clock (dclk 12), then generates an external clock (clkout 13) through a buffer (BUF 15). The external clock signal is fed back to the timing-control circuit (SMDF 14) and used to generate an internal clock signal so as to synchronize the external clock signal in phase with the reference clock signal. The timing-control circuit is provided with a circuit (FDA 21, MCC 22) for detecting a phase difference between the internal clock signal and the external clock signal, as well as a delay circuit (DCL 24) for controlling a delay time, so that the delay circuit (DCL 24) can change the delay time according to the detected phase difference.

公开(公告)号：US08132063B2

公开(公告)日：2012-03-06

申请号：US13191442

申请日：2011-07-26

申请人： Motoyasu Terao ,  Satoru Hanzawa ,  Hitoshi Kume ,  Minoru Ogushi ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Norikatsu Takaura

发明人： Motoyasu Terao ,  Satoru Hanzawa ,  Hitoshi Kume ,  Minoru Ogushi ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Norikatsu Takaura

IPC分类号： G11C29/00

CPC分类号： G11C13/0064 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50008 ,  G11C2013/0054 ,  G11C2213/72

摘要： To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

摘要翻译： 为了实现低功耗的快速且高度可靠的相变存储器系统，半导体器件包括：存储器件，其包括具有包括多个第一存储器单元的第一区域的第一存储器阵列和包括多个第一存储器单元的第二区域 第二存储单元; 控制器，其耦合到所述存储器设备以向所述存储器设备发出命令; 以及用于存储多个试写条件的条件表。 控制器基于存储在条件表中的多个试写条件，在多个第二存储单元中执行多次尝试写入，并且基于试写的结果来确定多个第一存储单元中的写入条件。 存储器件基于从控制器指示的写入条件在多个第一存储器单元中执行写入。

公开(公告)号：US07885102B2

公开(公告)日：2011-02-08

申请号：US12377271

申请日：2006-09-15

申请人： Satoru Hanzawa ,  Yoshikazu Iida

发明人： Satoru Hanzawa ,  Yoshikazu Iida

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/004 ,  G11C2213/79

摘要： In a memory array MCA which includes memory cells MC each having a variable-resistance-based memory device RQ and a select transistor MQ, an object is to receive a fixed quantity of storage data for a short time, and to realize writing operation to the memory cell, with suppressed peak current. In order to achieve the object, the data bus occupation time in rewriting operation is shortened by using plural sense amplifiers and storing storage data temporarily, and plural programming circuits are provided and activated using the control signals with different phases. By the above, the phase change memory system with low current consumption can be realized, without causing degradation of the utilization ratio of the data bus.

摘要翻译： 在包括具有可变电阻的存储器件RQ和选择晶体管MQ的存储单元MC的存储器阵列MCA中，目的是在短时间内接收固定量的存储数据，并且实现对 存储单元，具有抑制的峰值电流。 为了实现该目的，通过使用多个读出放大器和临时存储存储数据来缩短重写操作中的数据总线占用时间，并且使用具有不同相位的控制信号来提供和激活多个编程电路。 通过上述，可以实现具有低电流消耗的相变存储器系统，而不会降低数据总线的利用率。

公开(公告)号：US07505299B2

公开(公告)日：2009-03-17

申请号：US11976531

申请日：2007-10-25

申请人： Riichiro Takemura ,  Satoru Akiyama ,  Satoru Hanzawa ,  Tomonori Sekiguchi ,  Kazuhiko Kajigaya

发明人： Riichiro Takemura ,  Satoru Akiyama ,  Satoru Hanzawa ,  Tomonori Sekiguchi ,  Kazuhiko Kajigaya

IPC分类号： G11C5/06 ,  G11C11/24 ,  G11C7/02 ,  G11C8/00

CPC分类号： G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10873

摘要： A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.

摘要翻译： 提供了可以实现高速操作或高度集成并同时实现高速操作的半导体存储器件。 晶体管设置在扩散层区域的两侧，用于存储信息的电容器被连接到，并且每个晶体管的其它扩散层区域连接到相同的位线。 当访问存储器单元时，两个晶体管被激活并且读取该信息。 当对存储单元进行写操作时，使用两个晶体管，并将电荷写入电容器。

公开(公告)号：US20060158924A1

公开(公告)日：2006-07-20

申请号：US11280170

申请日：2005-11-17

申请人： Tomonori Sekiguchi ,  Satoru Akiyama ,  Riichiro Takemura ,  Satoru Hanzawa ,  Kazuhiko Kajigaya

发明人： Tomonori Sekiguchi ,  Satoru Akiyama ,  Riichiro Takemura ,  Satoru Hanzawa ,  Kazuhiko Kajigaya

IPC分类号： G11C11/24

CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4074 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10882

摘要： A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold voltage, MVT: mid threshold voltage, HVT: high threshold voltage) of a memory cell transistor is written into a storage node of a capacitor via the memory cell transistor. Thereafter, when a plate line connected to a plate side of the capacitor is driven from voltage VPL to voltage VPH and the voltage of the storage node is increased due to coupling, the voltage VDL of the bit line is reduced to the voltage VDP, and the voltage excessively written into the storage node is reduced in accordance with a level of a threshold voltage of the memory cell transistor, thereby reducing a variation in the voltage of the storage node due to a variation in the threshold voltage.

摘要翻译： 从外部输入写命令，位线的电压变为VDL和VSS，以及根据存储单元的阈值电压（LVT：低阈值电压，MVT：中间阈值电压，HVT：高阈值电压）的电压 晶体管经由存储单元晶体管写入电容器的存储节点。 此后，当连接到电容器的板侧的板线从电压VPL驱动到电压VPH并且存储节点的电压由于耦合而增加时，位线的电压VDL被降低到电压VDP，并且 根据存储单元晶体管的阈值电压的电平降低过度写入存储节点的电压，从而减小由于阈值电压的变化引起的存储节点的电压的变化。

公开(公告)号：US08830740B2

公开(公告)日：2014-09-09

申请号：US13814104

申请日：2011-08-26

申请人： Yoshitaka Sasago ,  Hiroyuki Minemura ,  Takashi Kobayashi ,  Toshimichi Shintani ,  Satoru Hanzawa ,  Masaharu Kinoshita

发明人： Yoshitaka Sasago ,  Hiroyuki Minemura ,  Takashi Kobayashi ,  Toshimichi Shintani ,  Satoru Hanzawa ,  Masaharu Kinoshita

IPC分类号： G11C11/00 ,  H01L47/00 ,  G11C13/00

CPC分类号： G11C13/0004 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/75 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233

摘要： The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.

摘要翻译： 本发明的目的是提高相变存储器的重写传输速率和可靠性。 为了实现该目的，在串行（2）和位线（3）之间串联提供多个相变存储单元（SMC或USMC），并且具有并联连接的选择元件和存储元件 彼此完全设置，之后，与数据模式对应的单元的一部分被重置。 或者，执行相反的操作。

公开(公告)号：US08614922B2

公开(公告)日：2013-12-24

申请号：US13327585

申请日：2011-12-15

申请人： Satoru Hanzawa

发明人： Satoru Hanzawa

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1039 ,  G11C7/1042 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2207/2209 ,  G11C2207/2245 ,  G11C2211/5623 ,  G11C2211/5624

摘要： A semiconductor storage apparatus provides a large capacity phase-change memory possessing high speed operation, low electrical current, and high-reliability. During the period that a read-out start signal is activated in the memory region control circuit, and the block of pairs of sense-latch and write driver is performing the verify read in the upper section memory region, the write enable signals in the memory region control circuit are activated and the block of pairs of sense-latch and write driver performs rewrite operation of the data in the lower section memory region. This type of operation allows cancelling out the time required for the verify read and the time required for the time-division write operation by performing the verify read in one memory region, while performing time-division rewrite in other memory region, to achieve both higher reliability rewrite operation along with suppressing the rewrite operation peak electrical current.

摘要翻译： 半导体存储装置提供具有高速运行，低电流和高可靠性的大容量相变存储器。 在存储器区域控制电路中激活读出开始信号的期间，并且读出驱动器对的块对在上部存储区进行验证读取，存储器中的写使能信号 区域控制电路被激活，并且一对感测锁存器和写入驱动器执行下部存储器区域中的数据的重写操作。 这种类型的操作允许通过在一个存储器区域中执行验证读取同时在其他存储器区域中执行时分重写来消除验证读取所需的时间和时分写入操作所需的时间，以实现更高的 可靠性重写操作以及抑制重写操作峰值电流。

公开(公告)号：US08563961B2

公开(公告)日：2013-10-22

申请号：US13515435

申请日：2010-12-13

申请人： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikastsu Takaura

发明人： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikastsu Takaura

IPC分类号： H01L47/00

CPC分类号： H01L45/1666 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

摘要： Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.

摘要翻译： 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N> = 1）个第一栅极间绝缘层（11-15）和N个第一半导体 层（21p-24p）在基板的高度方向交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。