公开(公告)号：US20170038826A1

公开(公告)日：2017-02-09

申请号：US15299579

申请日：2016-10-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuji NISHIJIMA ,  Hidetomo KOBAYASHI ,  Tomoaki ATSUMI ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

Abstract: A microcontroller which operates in a low power consumption mode is provided. A microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register in the peripheral circuit is provided in an interface with a bus line. A power gate for controlling supply control is provided. The microcontroller can operate not only in a normal operation mode where all circuits are active, but also in a low power consumption mode where some of the circuits are active. A volatile memory and nonvolatile memory are provided in a register, such as a register of the CPU. Data in the volatile memory is backed up in the nonvolatile memory before the power supply is stopped. In the case where the operation mode returns to the normal mode, when power supply is started again, data in the nonvolatile memory is written back into the volatile memory.

Abstract translation: 提供以低功耗模式工作的微控制器。 微控制器包括CPU，存储器和诸如定时器电路的外围电路。 外围电路中的寄存器设置在与总线线路的接口中。 提供用于控制电源控制的电源门。 微控制器不仅可以在所有电路都有效的正常工作模式下工作，而且还可以在一些电路处于活动状态的低功耗模式下工作。 在诸如CPU的寄存器的寄存器中提供易失性存储器和非易失性存储器。 在电源停止之前，易失性存储器中的数据被备份在非易失性存储器中。 在操作模式返回到正常模式的情况下，当再次开始供电时，非易失性存储器中的数据被写回到易失性存储器中。

公开(公告)号：US20170033110A1

公开(公告)日：2017-02-02

申请号：US15292362

申请日：2016-10-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka SHIONOIRI ,  Hiroyuki MIYAKE ,  Kiyoshi KATO

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/786

Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

Abstract translation: 本发明的目的是提供一种能够抑制功耗的存储器件和包括存储器件的半导体器件。 作为用作保持蓄积在用作存储元件的晶体管中的电荷的开关元件，为存储器件中的每个存储单元提供包括作为有源层的氧化物半导体膜的晶体管。 用作存储元件的晶体管具有第一栅电极，第二栅电极，位于第一栅电极和第二栅电极之间的半导体膜，位于第一栅电极和半导体膜之间的第一绝缘膜， 位于第二栅电极和半导体膜之间的第二绝缘膜，以及与半导体膜接触的源电极和漏电极。

公开(公告)号：US20160267950A1

公开(公告)日：2016-09-15

申请号：US15159919

申请日：2016-05-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Kiyoshi KATO

IPC: G11C5/14 ,  H01L27/108 ,  H01L27/12 ,  H01L23/528 ,  H01L29/786 ,  G11C11/408 ,  G11C11/24 ,  H01L27/06 ,  G11C11/409 ,  H01L27/105 ,  G11C8/10 ,  G11C8/08 ,  G11C11/56 ,  H01L29/24 ,  G11C7/12

CPC classification number: G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C8/16 ,  G11C11/24 ,  G11C11/405 ,  G11C11/4087 ,  G11C11/409 ,  G11C11/565 ,  G11C2207/108 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/1082 ,  H01L27/10826 ,  H01L27/10855 ,  H01L27/10858 ,  H01L27/10873 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/786 ,  H01L29/7869

Abstract: A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line. Write operation is performed in such a manner that first data is supplied to a gate of the fifth transistor through the first transistor; the first transistor is turned off; second data is supplied to a second electrode of the capacitor through the second transistor to convert the first data into third data; and the second electrode of the capacitor are made electrically floating. The second electrode of the capacitor is initialized to GND through the third transistor. Read operation is performed by charging or discharging the bit line through the fourth transistor and the fifth transistor. The first to third transistors are preferably oxide semiconductor transistors.

公开(公告)号：US20160260718A1

公开(公告)日：2016-09-08

申请号：US15157565

申请日：2016-05-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H01L27/105 ,  H01L29/24 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L27/1052 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/79 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

公开(公告)号：US20160217848A1

公开(公告)日：2016-07-28

申请号：US14993375

申请日：2016-01-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Wataru UESUGI ,  Kiyoshi KATO ,  Tatsuya ONUKI

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G06F2212/221 ,  G11C5/14 ,  G11C5/148 ,  G11C11/418 ,  G11C14/0054 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/02631 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device having a novel structure. To provide a semiconductor device excellent in reducing power consumption. A memory cell including an SRAM capable of backing up data to the nonvolatile memory and a peripheral circuit of the memory cell are configured to offer different power gating states. In a first period, which is extremely short, the bit line is brought into an electrically floating state by turning off the switch. In a second period, which is longer than the first period, power gating is performed on the memory cell. In a third period, which is longer than the second period, power gating is performed on the memory cell and the peripheral circuits.

Abstract translation: 提供具有新颖结构的半导体器件。 提供一种降低功耗的半导体器件。 包括能够将数据备份到非易失性存储器的SRAM和存储器单元的外围电路的存储单元被配置为提供不同的功率门控状态。 在非常短的第一时段中，通过关闭开关使位线进入电浮动状态。 在比第一期间长的第二期间，对存储单元进行电力门控。 在比第二时段长的第三时段中，对存储单元和外围电路进行功率门控。

公开(公告)号：US20160172010A1

公开(公告)日：2016-06-16

申请号：US14963434

申请日：2015-12-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO

IPC: G11C5/10

CPC classification number: G11C5/10 ,  G11C5/06 ,  G11C7/14 ,  G11C11/24 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/419 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5006

Abstract: To provide a small, highly reliable memory device with a large storage capacity. A semiconductor device includes a circuit for retaining data and a circuit for reading data. The circuit for retaining data includes a transistor and a capacitor. The circuit for reading data is configured to supply a potential to the circuit for retaining data and read a potential from the circuit for retaining data. The circuit for retaining data and the circuit for reading data are provided in different layers, so that the semiconductor device with a large storage capacity is manufactured.

Abstract translation: 提供具有大存储容量的小型，高度可靠的存储器件。 半导体器件包括用于保留数据的电路和用于读取数据的电路。 用于保留数据的电路包括晶体管和电容器。 用于读取数据的电路被配置为向电路提供用于保留数据的电位并从电路读取用于保留数据的电位。 用于保留数据的电路和用于读取数据的电路设置在不同的层中，从而制造具有大存储容量的半导体器件。

公开(公告)号：US20160155480A1

公开(公告)日：2016-06-02

申请号：US14951937

申请日：2015-11-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroki INOUE ,  Kiyoshi KATO ,  Takanori MATSUZAKI

IPC: G11C5/10 ,  H01L27/108 ,  G11C7/12 ,  H01L27/06

CPC classification number: G11C5/10 ,  G11C7/12 ,  G11C11/405 ,  H01L21/8258 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225

Abstract: A semiconductor device capable of inhibiting incorrect data readout is provided. In a memory cell including a first transistor, a second transistor, and a third transistor, the potential of a fourth wiring is set to GND when data is written, and the potential is set to VDD when data is read out, for example. Note that the potential of a third wiring is set to GND when data is written and when data is read out, for example. When data is read out, the first transistor is off, so that a first capacitor and a fourth capacitor are connected in series. The potential of a second electrode of the second capacitor increases in this state, and thus part of charges accumulated in the second capacitor transfers to the first capacitor, so that the potential of a node increases.

Abstract translation: 提供能够抑制不正确的数据读出的半导体器件。 在包括第一晶体管，第二晶体管和第三晶体管的存储单元中，例如，当数据被写入时，第四布线的电位被设置为GND，并且例如在读出数据时将电位设置为VDD。 注意，例如，当写入数据和数据被读出时，第三布线的电位被设置为GND。 当读出数据时，第一晶体管截止，使得第一电容器和第四电容器串联连接。 在该状态下，第二电容器的第二电极的电位增加，因此累积在第二电容器中的电荷的一部分转移到第一电容器，使得节点的电位增加。

公开(公告)号：US20160104521A1

公开(公告)日：2016-04-14

申请号：US14872535

申请日：2015-10-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Kiyoshi KATO ,  Wataru UESUGI ,  Takahiko ISHIZU

IPC: G11C11/4091

CPC classification number: G11C11/4091 ,  G11C5/025 ,  G11C7/02 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2213/71 ,  H01L27/10808

Abstract: A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.

Abstract translation: 提供具有低功耗的半导体器件或具有减小的面积的半导体器件。 半导体器件包括具有第一存储单元和第二存储单元的单元阵列; 以及包括第一读出放大器和第二读出放大器的读出放大器电路。 单元阵列位于读出放大器电路之上。 第一读出放大器通过第一布线BL与第一存储单元电连接。 第二读出放大器通过第二布线BL与第二存储单元电连接。 第一读出放大器和第二读出放大器电连接到布线GBL。 感测放大器电路被配置为选择第一布线BL的电位和第二布线BL的电位中的一个，并将所选择的电位输出到布线GBL。

公开(公告)号：US20160056298A1

公开(公告)日：2016-02-25

申请号：US14930081

申请日：2015-11-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Masakazu MURAKAMI

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/45 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/45

Abstract: A semiconductor device with significantly low off-state current is provided. An oxide semiconductor material in which holes have a larger effective mass than electrons is used. A transistor is provided which includes a gate electrode layer, a gate insulating layer, an oxide semiconductor layer including a hole whose effective mass is 5 or more times, preferably 10 or more times, further preferably 20 or more times that of an electron in the oxide semiconductor layer, a source electrode layer in contact with the oxide semiconductor layer, and a drain electrode layer in contact with the oxide semiconductor layer.

公开(公告)号：US20150381174A1

公开(公告)日：2015-12-31

申请号：US14842899

申请日：2015-09-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO

IPC: H03K19/00 ,  H01L29/24 ,  H01L29/04 ,  G06F1/32

CPC classification number: H03K19/0008 ,  G06F1/32 ,  H01L29/045 ,  H01L29/24 ,  H03K19/0013

Abstract: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.

Abstract translation: 为了降低功耗，具有基于输入信号进行逻辑运算处理的功能的运算电路，将根据逻辑运算处理结果存储的电位存储为存储数据，并输出具有值的信号 对应于存储的数据作为输出信号。 算术电路包括执行逻辑运算处理的运算部，控制是否设定了与逻辑运算处理结果对应的电位的第一电位的第一场效应晶体管，以及控制是否 输出信号数据的电位被设定为作为参考电位的第二电位。