公开(公告)号：US20180350997A1

公开(公告)日：2018-12-06

申请号：US16044600

申请日：2018-07-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro TANAKA ,  Mitsuhiro ICHIJO ,  Toshiya ENDO ,  Akihisa SHIMOMURA ,  Yuji EGI ,  Sachiaki TEZUKA ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/7869 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78606 ,  H01L29/78648

Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.

公开(公告)号：US20180277533A1

公开(公告)日：2018-09-27

申请号：US15991195

申请日：2018-05-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro TANAKA ,  Yutaka OKAZAKI

IPC: H01L27/07 ,  H01G4/008 ,  H01G4/10 ,  H01G4/40 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L29/94 ,  H05K1/18

CPC classification number: H01L27/0733 ,  H01G4/008 ,  H01G4/105 ,  H01G4/40 ,  H01L21/8258 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/66477 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696 ,  H01L29/94 ,  H05K1/18 ,  H05K2201/10015 ,  H05K2201/10083 ,  H05K2201/10166

Abstract: A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor.

公开(公告)号：US20180182899A1

公开(公告)日：2018-06-28

申请号：US15900845

申请日：2018-02-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Hideomi SUZAWA ,  Sachiaki TEZUKA ,  Tetsuhiro TANAKA ,  Toshiya ENDO ,  Mitsuhiro ICHIJO

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/8258 ,  H01L29/423 ,  H01L27/12 ,  H01L27/092 ,  H01L27/06 ,  H01L29/49

CPC classification number: H01L29/78648 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.

公开(公告)号：US20170294542A1

公开(公告)日：2017-10-12

申请号：US15632764

申请日：2017-06-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tetsuhiro TANAKA ,  Akihisa SHIMOMURA ,  Yasumasa YAMANE ,  Ryo TOKUMARU ,  Yuhei SATO ,  Kazuhiro TSUTSUI

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L29/7869 ,  C23C14/08 ,  C23C14/3414 ,  H01L21/02266 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A transistor with stable electrical characteristics is provided. The transistor includes a first insulator over a substrate; first to third oxide insulators over the first insulator; a second insulator over the third oxide insulator; a first conductor over the second insulator; and a third insulator over the first conductor. An energy level of a conduction band minimum of each of the first and second oxide insulators is closer to a vacuum level than that of the oxide semiconductor is. An energy level of a conduction band minimum of the third oxide insulator is closer to the vacuum level than that of the second oxide insulator is. The first insulator contains oxygen. The number of oxygen molecules released from the first insulator measured by thermal desorption spectroscopy is greater than or equal to 1E14 molecules/cm2 and less than or equal to 1E16 molecules/cm2.

公开(公告)号：US20170012138A1

公开(公告)日：2017-01-12

申请号：US15270064

申请日：2016-09-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Tetsuhiro TANAKA ,  Yuhei SATO ,  Sachiaki TEZUKA ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/78648 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/41733 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided. A transistor having small current in an off state (in a non-conductive state) is provided. A semiconductor device including such a transistor is provided. A first electrode is formed over a substrate, a first insulating layer is formed adjacent to a side surface of the first electrode, and a second insulating layer is formed to cover the first insulating layer and be in contact with at least part of a surface of the first electrode. The surface of the first electrode is formed of a conductive material that does not easily transmit an impurity element. The second insulating layer is formed of an insulating material that does not easily transmit an impurity element. An oxide semiconductor layer is formed over the first electrode with a third insulating layer provided therebetween.

Abstract translation: 提供具有高场效应迁移率的晶体管。 提供具有稳定电特性的晶体管。 提供了处于断开状态（非导通状态）的小电流的晶体管。 提供了包括这种晶体管的半导体器件。 第一电极形成在衬底上，第一绝缘层与第一电极的侧表面相邻地形成，并且形成第二绝缘层以覆盖第一绝缘层并与第一绝缘层的至少一部分表面接触 第一个电极。 第一电极的表面由不容易透过杂质元素的导电材料形成。 第二绝缘层由不容易透过杂质元素的绝缘材料形成。 在第一电极上形成氧化物半导体层，其间设置有第三绝缘层。

公开(公告)号：US20170012135A1

公开(公告)日：2017-01-12

申请号：US15211218

申请日：2016-07-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro TANAKA ,  Toshihiko TAKEUCHI ,  Yasumasa YAMANE

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/49 ,  H01L29/51

Abstract: Provided is a semiconductor device having a structure with which a decrease in electrical characteristics that becomes more significant with miniaturization can be suppressed. The semiconductor device includes a first oxide semiconductor film, a gate electrode overlapping with the first oxide semiconductor film, a first gate insulating film between the first oxide semiconductor film and the gate electrode, and a second gate insulating film between the first gate insulating film and the gate electrode. In the first gate insulating film, a peak appears at a diffraction angle 2θ of around 28° by X-ray diffraction. A band gap of the first oxide semiconductor film is smaller than a band gap of the first gate insulating film, and the band gap of the first gate insulating film is smaller than a band gap of the second gate insulating film.

Abstract translation: 提供一种半导体器件，其具有可以抑制随着小型化而变得更显着的电特性的降低的结构。 半导体器件包括第一氧化物半导体膜，与第一氧化物半导体膜重叠的栅电极，第一氧化物半导体膜和栅极之间的第一栅极绝缘膜，以及在第一栅极绝缘膜和第二栅极绝缘膜之间的第二栅极绝缘膜 栅电极。 在第一栅极绝缘膜中，通过X射线衍射在约28°的衍射角2θ出现峰。 第一氧化物半导体膜的带隙小于第一栅极绝缘膜的带隙，第一栅极绝缘膜的带隙小于第二栅极绝缘膜的带隙。

公开(公告)号：US20160284856A1

公开(公告)日：2016-09-29

申请号：US15077029

申请日：2016-03-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Akihisa SHIMOMURA ,  Tetsuhiro TANAKA ,  Masayuki KIMURA ,  Ryo TOKUMARU ,  Daisuke MATSUBAYASHI ,  Yasumasa YAMANE

IPC: H01L29/786 ,  G02F1/1368 ,  H01L27/32 ,  H01L29/24 ,  H01L27/12

CPC classification number: H01L29/7869 ,  G02F1/1368 ,  H01L27/1225 ,  H01L27/3262 ,  H01L29/24 ,  H01L29/78603

Abstract: A semiconductor device including a miniaturized transistor is provided. The semiconductor device includes a first insulator, a second insulator, a semiconductor, and a conductor. The semiconductor is over the first insulator. The second insulator is over the semiconductor. The conductor is over the second insulator. The semiconductor includes a first region, a second region, and a third region. The first region is a region where the semiconductor overlaps with the conductor. Each of the second region and the third region is a region where the semiconductor does not overlap with the conductor. The second region and the third region each have a region with a spinel crystal structure.

Abstract translation: 提供了包括小型化晶体管的半导体器件。 半导体器件包括第一绝缘体，第二绝缘体，半导体和导体。 半导体在第一绝缘体之上。 第二绝缘体在半导体上。 导体在第二绝缘体之上。 半导体包括第一区域，第二区域和第三区域。 第一区域是半导体与导体重叠的区域。 第二区域和第三区域中的每一个都是半导体不与导体重叠的区域。 第二区域和第三区域各自具有尖晶石晶体结构的区域。

公开(公告)号：US20160240690A1

公开(公告)日：2016-08-18

申请号：US15137621

申请日：2016-04-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Tetsuhiro TANAKA

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/78693 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02581 ,  H01L21/02617 ,  H01L21/02631 ,  H01L21/32139 ,  H01L27/1225 ,  H01L29/26 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78 ,  H01L29/78606 ,  H01L29/7869

Abstract: A semiconductor device in which an increase in oxygen vacancies in an oxide semiconductor layer can be suppressed is provided. A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor device includes an oxide semiconductor layer in a channel formation region, and by the use of an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer, oxygen of the oxide insulating film or the gate insulating film is supplied to the oxide semiconductor layer. Further, a conductive nitride is used for a metal film of a source electrode layer and a drain electrode layer, whereby diffusion of oxygen to the metal film is suppressed.

Abstract translation: 提供了可以抑制氧化物半导体层中氧空位增加的半导体器件。 提供了具有良好电气特性的半导体器件。 提供了一种高度可靠的半导体器件。 半导体器件包括在沟道形成区域中的氧化物半导体层，并且通过使用氧化物半导体层下方并与氧化物半导体层接触的氧化物绝缘膜和与氧化物半导体层接触的栅绝缘膜， 氧化物绝缘膜或栅极绝缘膜被提供给氧化物半导体层。 此外，导电氮化物用于源电极层和漏电极层的金属膜，从而抑制氧向金属膜的扩散。

公开(公告)号：US20160056043A1

公开(公告)日：2016-02-25

申请号：US14829029

申请日：2015-08-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro TANAKA ,  Ryo TOKUMARU ,  Yasumasa YAMANE ,  Akihisa SHIMOMURA ,  Naoki OKUNO

IPC: H01L21/28 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66742 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78648 ,  H01L29/7869

Abstract: To provide a semiconductor device including an oxide semiconductor layer with high and stable electrical characteristics, the semiconductor device is manufactured by forming a first insulating layer, forming oxide over the first insulating layer and then removing the oxide n times (n is a natural number), forming an oxide semiconductor layer over the first insulating layer, forming a second insulating layer over the oxide semiconductor layer, and forming a conductive layer over the second insulating layer. Alternatively, the semiconductor device is manufactured by forming the oxide semiconductor layer over the first insulating layer, forming the second insulating layer over the oxide semiconductor layer, forming the oxide over the second insulating layer and then removing the oxide n times (n is a natural number), and forming the conductive layer over the second insulating layer.

Abstract translation: 为了提供包括具有高且稳定的电特性的氧化物半导体层的半导体器件，通过形成第一绝缘层，在第一绝缘层上形成氧化物，然后去除氧化物n次（n为自然数）来制造半导体器件， 在所述第一绝缘层上形成氧化物半导体层，在所述氧化物半导体层上形成第二绝缘层，以及在所述第二绝缘层上形成导电层。 或者，半导体器件通过在第一绝缘层上形成氧化物半导体层而形成，在氧化物半导体层上形成第二绝缘层，在第二绝缘层上形成氧化物，然后去除氧化物n次（n是自然的 数量），并且在第二绝缘层上形成导电层。

公开(公告)号：US20150349130A1

公开(公告)日：2015-12-03

申请号：US14723624

申请日：2015-05-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuki TANEMURA ,  Tetsuhiro TANAKA ,  Kosei NODA

IPC: H01L29/786 ,  H01L29/51 ,  H01L29/792 ,  H01L27/12 ,  H01L27/088

CPC classification number: H01L29/7869 ,  H01L22/14 ,  H01L22/20 ,  H01L27/0883 ,  H01L27/1104 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78696 ,  H01L29/792

Abstract: Threshold voltage adjustment method of a semiconductor device is provided. In a semiconductor device in which at least one of transistors included in an inverter includes a semiconductor, a source electrode or a drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer provided between the gate electrode and the semiconductor, the potential of the gate electrode of the transistor that is higher than those of the source electrode and the drain electrode is held for a short time of 5 s or shorter, whereby electrons are trapped in the charge trap layer and the threshold voltage is increased. At this time, when the potential differences between the gate electrode and the source electrode, and the gate electrode and the drain electrode are different from each other, the threshold voltage of the transistor of the semiconductor device becomes appropriate.

Abstract translation: 提供半导体器件的阈值电压调整方法。 在其中包括在反相器中的至少一个晶体管包括半导体，与半导体电连接的源电极或漏电极，设置在栅电极和半导体之间的栅电极和电荷陷阱层的半导体器件中， 晶体管的栅电极的电位比源电极和漏电极的电位保持5秒以下的短时间，由此电子被捕获在电荷陷阱层中，并且阈值电压增加。 此时，当栅电极和源电极以及栅电极和漏电极之间的电位差彼此不同时，半导体器件的晶体管的阈值电压变得适当。