公开(公告)号：US20160099067A1

公开(公告)日：2016-04-07

申请号：US14506433

申请日：2014-10-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

IPC: G11C16/24 ,  G11C16/26 ,  G11C16/04 ,  G11C16/14

CPC classification number: G11C16/24 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

Abstract: A non-volatile memory device that a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. A negative charge pump circuit generates a first negative voltage. A control circuit receives a command signal and generates a plurality of control signals, in response thereto and applies the first negative voltage to the word line of the unselected memory cells. During the operations of program, read or erase, a negative voltage can be applied to the word lines of the unselected memory cells.

公开(公告)号：US09245638B2

公开(公告)日：2016-01-26

申请号：US14216776

申请日：2014-03-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Elizabeth A. Cuevas ,  Yuri Tkachev ,  Mandana Tadayoni ,  Henry A. Om'mani

IPC: G11C16/04 ,  G11C16/26 ,  H01L27/115 ,  G11C16/14

CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C16/14 ,  H01L27/115

Abstract: A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the fir region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.

Abstract translation: 一种操作存储单元的方法，所述存储单元包括在衬底中间隔开的沟道区域中的第一和第二区域，设置在所述沟道区域和所述冷杉区域上方的浮置栅极，设置在所述沟道区域上方且横向邻近 浮动栅极，其具有设置在浮置栅极上的部分，以及耦合栅极，设置在第一区域上并且横向邻近浮动栅极。 擦除存储单元的方法包括向控制栅极施加正电压，向耦合栅极施加负电压。 读取存储单元的方法包括向控制栅极，耦合栅极以及第一和第二区域之一施加正电压。

公开(公告)号：US12198043B2

公开(公告)日：2025-01-14

申请号：US18522153

申请日：2023-11-28

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten ,  Nhan Do

IPC: G06N3/065 ,  G06F3/06 ,  G06F17/16 ,  G06N3/08 ,  G11C27/02

Abstract: In one example, a circuit comprises an input transistor comprising a first terminal, a second terminal coupled to ground, and a gate; a capacitor comprising a first terminal and a second terminal; an output transistor comprising a first terminal providing an output current, a second terminal coupled to ground, and a gate; a first switch; and a second switch; wherein in a first mode, the first switch is closed and couples an input current to the first terminal of the input transistor and the gate of the input transistor and the second switch is closed and couples the first terminal of the input transistor to the first terminal of the capacitor and the gate of the output transistor, and in a second mode, the first switch is open and the second switch is open and the capacitor discharges into the gate of the output transistor.

公开(公告)号：US12131786B2

公开(公告)日：2024-10-29

申请号：US18104228

申请日：2023-01-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Louisa Schneider ,  Xian Liu ,  Steven Lemke ,  Parviz Ghazavi ,  Jinho Kim ,  Henry A. Om'Mani ,  Hieu Van Tran ,  Nhan Do

IPC: G11C5/06 ,  G11C16/16 ,  H01L23/48 ,  H01L29/423 ,  H10B41/10 ,  H10B41/27

CPC classification number: G11C16/16 ,  H01L23/481 ,  H01L29/42328 ,  H10B41/10 ,  H10B41/27

Abstract: A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region. A strap region is disposed between first and second pluralities of the columns. For one memory cell row, a dummy floating gate is disposed in the strap region, an erase gate line electrically connects together the erase gates of the memory cells in the one row and in the first plurality of columns, wherein the erase gate line is aligned with the dummy floating gate with a row direction gap between the erase gate line and the dummy floating gate.

公开(公告)号：US12112798B2

公开(公告)日：2024-10-08

申请号：US18123918

申请日：2023-03-20

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Farnood Merrikh Bayat ,  Xinjie Guo ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten

IPC: G11C11/54 ,  G06F3/06 ,  G06N3/04 ,  G06N3/045 ,  G06N3/063 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C29/38

CPC classification number: G11C11/54 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06N3/04 ,  G06N3/045 ,  G06N3/063 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3436 ,  G11C29/38

Abstract: Numerous examples are disclosed for an output block coupled to a non-volatile memory array in a neural network and associated methods. In one example, a circuit for converting a current in a neural network into an output voltage comprises a non-volatile memory cell comprises a word line terminal, a bit line terminal, and a source line terminal, wherein the bit line terminal receives the current; and a switch for selectively coupling the word line terminal to the bit line terminal; wherein when the switch is closed, the current flows into the non-volatile memory cell and the output voltage is provided on the bit line terminal.

公开(公告)号：US20240274186A1

公开(公告)日：2024-08-15

申请号：US18644840

申请日：2024-04-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C11/54 ,  G06N3/045 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L29/423 ,  H01L29/788 ,  H10B41/30

CPC classification number: G11C11/54 ,  G06N3/045 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7883 ,  H10B41/30

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, fourth lines each electrically connect the drain regions in one of the memory cell columns, and a plurality of transistors each electrically connected in series with one of the fourth lines. The synapses receive a first plurality of inputs as electrical voltages on gates of the transistors, and provide a first plurality of outputs as electrical currents on the third lines.

公开(公告)号：US11915747B2

公开(公告)日：2024-02-27

申请号：US17856839

申请日：2022-07-01

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  G11C16/10 ,  G06N3/065

CPC classification number: G11C11/54 ,  G06N3/065 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  G11C2216/04

Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, an analog neural memory system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to erase gate terminals of a word of non-volatile memory cells.

公开(公告)号：US20230325645A1

公开(公告)日：2023-10-12

申请号：US17848371

申请日：2022-06-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Mark Reiten ,  Nhan Do

IPC: G06N3/063 ,  G06F17/16

CPC classification number: G06N3/063 ,  G06F17/16

Abstract: Numerous examples are disclosed of an artificial neural network comprising a three-dimensional integrated circuit. In one embodiment, a three-dimensional integrated circuit for use in an artificial neural network comprises a first die comprising a first vector by matrix multiplication array and a first input multiplexor, the first die located on a first vertical layer; a second die comprising an input circuit, the second die located on a second vertical layer different than the first vertical layer; and one or more vertical interfaces coupling the first die and the second die; wherein during a read operation, the input circuit provides an input signal to the first input multiplexor over at least one of the one or more vertical interfaces, the first input multiplexor applies the input signal to one or more rows in the first vector by matrix multiplication array, and the first vector by matrix multiplication array generates an output.

公开(公告)号：US20230292504A1

公开(公告)日：2023-09-14

申请号：US17834746

申请日：2022-06-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Zhuoqiang Jia ,  Leo Xing ,  Xian Liu ,  Serguei Jourba ,  Nhan Do

IPC: H01L27/11531 ,  H01L29/423 ,  H01L21/28 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L27/11531 ,  H01L29/42328 ,  H01L29/40114 ,  H01L29/7883 ,  H01L29/66825

Abstract: A method includes recessing an upper surface of a substrate in first and second areas relative to a third area, forming a first conductive layer in the first area, forming a second conductive layer in the three areas, selectively removing the first and second conductive layers in the first area, while maintaining the second conductive layer in the second and third areas, leaving pairs of stack structures in the first area respectively having a control gate of the second conductive layer and a floating gate of the first conductive layer, forming a third conductive layer in the three areas, recessing the upper surface of the third conductive layer below tops of the stack structures and removing the third conductive layer from the second and third areas, removing the second conductive layer from the second and third areas, and forming blocks of metal material in the second and third areas.

公开(公告)号：US20230290864A1

公开(公告)日：2023-09-14

申请号：US17824812

申请日：2022-05-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/788 ,  H01L29/423 ,  H01L29/78 ,  H01L27/11556

CPC classification number: H01L29/66795 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823412 ,  H01L29/0847 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/42328 ,  H01L29/7851 ,  H01L27/11556

Abstract: A method of forming a device on a silicon substrate having first, second and third areas includes recessing an upper substrate surface in the first and third areas, forming an upwardly extending silicon fin in the second area, forming first source, drain and channel regions in the first area, forming second source, drain and channel regions in the fin, forming third source, drain and channel regions in the third area, forming a floating gate over a first portion of the first channel region using a first polysilicon deposition, forming an erase gate over the first source region and a device gate over the third channel region using a second polysilicon deposition, and forming a word line gate over a second portion of the first channel region, a control gate over the floating gate, and a logic gate over the second channel region using a metal deposition.