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76 条记录 (耗时 0.023 秒)

    Multiport memory
    52.
    发明授权
    Multiport memory 失效
    多端口内存

    公开(公告)号：US5138581A

    公开(公告)日：1992-08-11

    申请号：US577361

    申请日：1990-09-05

    申请人： Shinji Miyamoto ,  Shigeo Ohshima

    发明人： Shinji Miyamoto ,  Shigeo Ohshima

    IPC分类号： G11C11/401 ,  G11C7/10

    CPC分类号： G11C7/1075

    摘要： A multiport memory has a RAM port including a memory cell array having a plurality of memory cells arranged in a matrix form, sense amplifier circuit for sensing potential of a bit line after the storage potential has been transferred from the memory cells, restore circuit connected to the bit line for pulling up the potential of the bit line at the predetermined timing after sense operation has been started and a barrier circuit connected between the bit line and the sense amplifier circuit; and a SAM port including a data register, transfer gate and functional means for transferring serial data in the column direction. In this memory, the RAM port is connected to the SAM port by the transfer gate with the bit line directly connected to the data register, and the potentials at the bit line are amplified by the sense amplifier circuit and are directly transferred to the data register.

    摘要翻译： 多端口存储器具有包括具有以矩阵形式布置的多个存储单元的存储单元阵列的RAM端口，用于在从存储单元传送存储电位之后感测位线的电位的读出放大器电路，恢复电路连接到 用于在感测操作之后的预定定时提升位线的电位的位线和连接在位线和读出放大器电路之间的屏障电路; 以及包括数据寄存器，传送门和用于在列方向上传送串行数据的功能装置的SAM端口。 在该存储器中，RAM端口通过传输门连接到SAM端口，位线直接连接到数据寄存器，位线上的电位由读出放大器电路放大并直接传输到数据寄存器 。

    Semiconductor memory system
    53.
    发明授权
    Semiconductor memory system 失效
    半导体存储系统

    公开(公告)号：US5107464A

    公开(公告)日：1992-04-21

    申请号：US480902

    申请日：1990-02-16

    申请人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

    发明人： Hiroshi Sahara ,  Haruki Toda ,  Shigeo Ohshima

    IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/846

    摘要： In a semiconductor memory system of the serial column access type, a redundant column is used for replacing a defective column. Redundant data lines are connected to the redundant column through a redundant column selection gate. A defective address detection circuit detects the address of a defective column to enable the redundant column selection gate. An address counter is provided for a defective address detection circuit. A redundant column selection circuit selects the redundant column in response to a detection signal from the defective address detection circuit. A data line switching circuit switches, in redundant column select mode, the data lines connecting to a data input/output drive circuit from said regular data lines to the redundant data lines. With this circuit arrangement, in a redundant column select mode, the regular data lines are separated from the data input/output drive circuit. Therefore, even if a shift register constituting a regular column selection circuit operates and the defective column selection gate is enabled to set up a connection of the defective column to the regular data lines, the error data from the defective column is never output. Further, the shift register is operable irrespective of the defective column detection.

    Flip-flop circuit
    55.
    发明授权
    Flip-flop circuit 失效
    触发电路

    公开(公告)号：US4678934A

    公开(公告)日：1987-07-07

    申请号：US884629

    申请日：1986-07-11

    申请人： Koichi Magome ,  Haruki Toda ,  Hiroyuki Koinuma ,  Hiroshi Sahara ,  Kiminobu Suzuki ,  Shigeo Ohshima ,  Kenji Komatsu

    发明人： Koichi Magome ,  Haruki Toda ,  Hiroyuki Koinuma ,  Hiroshi Sahara ,  Kiminobu Suzuki ,  Shigeo Ohshima ,  Kenji Komatsu

    IPC分类号： G11C11/40 ,  G11C8/06 ,  H03K3/356 ,  H03K3/26 ,  G11C7/00 ,  H03K17/687 ,  H03K19/094

    CPC分类号： H03K3/356026 ,  G11C8/06

    摘要： A flip-flop circuit has a power terminal set at 5 V, first and second output terminals, a latch section for charging one of the first and second terminals to 5 V and discharging the other one of the first and second terminals to 0 V in accordance with an input signal, a first MOS transistor having a current path connected between the power and first output terminals, a second MOS transistor for charging the gate of the first MOS transistor while the potential of the second output terminal is changed from 5 V to 0 V, and a capacitor for bootstrapping the gate potential of the first MOS transistor to turn on the first MOS transistor. The flip-flop circuit further includes a third MOS transistor, having a current path connected between the gate of the first MOS transistor and the first output terminal and a gate connected to the first output terminal, for charging the gate of the first MOS transistor when the gate potential of the first MOS transistor is dropped a predetermined level in comparison with that of the first output terminal.

    摘要翻译： 触发器电路具有设置在5V的电源端子，第一和第二输出端子，用于将第一和第二端子中的一个充电至5V并将第一和第二端子中的另一个放电至0V的锁存部分 根据输入信号，具有连接在电源和第一输出端子之间的电流路径的第一MOS晶体管，第二MOS晶体管，用于对第一MOS晶体管的栅极充电，同时第二输出端子的电位从5V变为 0V，以及用于自举第一MOS晶体管的栅极电位以使第一MOS晶体管导通的电容器。 触发器电路还包括第三MOS晶体管，其具有连接在第一MOS晶体管的栅极和第一输出端子之间的电流路径和连接到第一输出端子的栅极，用于对第一MOS晶体管的栅极充电， 与第一输出端子相比，第一MOS晶体管的栅极电位下降到预定水平。

    METHOD OF PROGRAMMING A NON-VOLATILE MEMORY DEVICE
    59.
    发明申请
    METHOD OF PROGRAMMING A NON-VOLATILE MEMORY DEVICE 有权
    编程非易失性存储器件的方法

    公开(公告)号：US20080291716A1

    公开(公告)日：2008-11-27

    申请号：US12123827

    申请日：2008-05-20

    申请人： Takuya Futatsuyama ,  Koji Hosono ,  Toshiaki Edahiro ,  Naoya Tokiwa ,  Kazushige Kanda ,  Shigeo Ohshima

    发明人： Takuya Futatsuyama ,  Koji Hosono ,  Toshiaki Edahiro ,  Naoya Tokiwa ,  Kazushige Kanda ,  Shigeo Ohshima

    IPC分类号： G11C11/00

    CPC分类号： G11C11/36

    摘要： A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.

    摘要翻译： 一种使用由可变电阻元件形成并且设置在字线和位线之间的存储单元来编程非易失性存储器件的方法包括：预先对所选择的字线和所选择的位线以及未选择的字线和 非选择位线达到一定电压; 并且进一步对所选字线和未选择的位线进行充电，直到分别高于特定电压和编程块电压的编程电压，并同时对所选择的位线进行放电。

    SEMICONDUCTOR DEVICE, RELAY CHIP, AND METHOD FOR PRODUCING RELAY CHIP
    60.
    发明申请
    SEMICONDUCTOR DEVICE, RELAY CHIP, AND METHOD FOR PRODUCING RELAY CHIP 失效
    半导体器件，继电器芯片和生产继电器芯片的方法

    公开(公告)号：US20080054491A1

    公开(公告)日：2008-03-06

    申请号：US11851118

    申请日：2007-09-06

    申请人： Eiichi Makino ,  Shigeo Ohshima ,  Naohisa Okumura

    发明人： Eiichi Makino ,  Shigeo Ohshima ,  Naohisa Okumura

    IPC分类号： H01L23/50 ,  H05K1/00 ,  H05K3/10

    CPC分类号： H01L23/5385 ,  H01L23/13 ,  H01L23/5386 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/18 ,  H01L2223/5448 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  Y10T29/49162 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A semiconductor device according to the present invention includes a substrate including a plurality of first pads thereon; at least one semiconductor chip including a plurality of second pads; and at least one wiring chip including a plurality of third pads. A part of the plurality of second pads of the semiconductor chip is electrically connected to a part of the plurality of third pads of the wiring chip, and another part of the plurality of third pads of the wiring chip is electrically connected to a part of the plurality of first pads of the substrate. The plurality of third pads of the wiring chip are located along two adjacent sides of a wiring chip substrate of the wiring chip, and are connected to each other by a plurality of metal wires, sequentially from the third pads closest from a contact point of the two sides; The plurality of metal wires each include a first part drawn from each of the plurality of third pads located along a first side of the two sides inward the wiring chip so as to be parallel to, or so as to form an acute angle with, a second side of the two sides, a second part drawn from each of the plurality of third pads located along the second side inward the wiring chip so as to be parallel to, or so as to form an acute angle with, the first side, and a third part connecting the first part and the second part to each other in a straight manner. The plurality of metal wires are formed such that a wiring width of each metal wire, a wiring interval between each metal wire and a metal wire adjacent and outer thereto, and a wiring pitch which is a sum of each wiring width and a corresponding wiring interval are set so as to minimize a difference between wiring capacitances of each adjacent metal wires among the plurality of metal wires.

    摘要翻译： 根据本发明的半导体器件包括其上包括多个第一焊盘的衬底; 至少一个半导体芯片，包括多个第二焊盘; 以及包括多个第三焊盘的至少一个布线芯片。 半导体芯片的多个第二焊盘的一部分电连接到布线芯片的多个第三焊盘的一部分，并且布线芯片的多个第三焊盘的另一部分电连接到 多个基片的第一垫片。 布线芯片的多个第三焊盘沿着布线芯片的布线芯片基板的两个相邻侧布置，并且从多个金属布线彼此连接，从最接近 双方; 多个金属线各自包括从沿着两侧的第一侧向内布置的多个第三焊盘中的每一个的第一部分，其与平行于或与之形成锐角的第一部分 所述两侧的第二侧，从所述多个第三焊盘中的每一个沿着所述第二侧向内布置在所述布线芯片上的第二部分，以与所述第一侧平行或与之形成锐角;以及 将第一部分和第二部分以直线方式彼此连接的第三部分。 多个金属线被形成为使得每个金属线的布线宽度，每个金属布线和与其外部的金属线之间的布线间隔以及布线间距是每个布线宽度和相应的布线间隔之和的布线间距 被设置为使多个金属线中的每个相邻的金属线的布线电容之间的差最小化。