公开(公告)号：US08735280B1

公开(公告)日：2014-05-27

申请号：US13724342

申请日：2012-12-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Fu Yeh ,  Hsiang-Huan Lee ,  Chao-Hsien Peng ,  Hsien-Chang Wu

IPC分类号： H01L21/4763 ,  H01L21/027 ,  H01L21/768

CPC分类号： H01L21/76892 ,  B82Y40/00 ,  H01L21/02115 ,  H01L21/02697 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  H01L2924/00

摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A conductive layer is deposited on the substrate. A patterned hard mask is formed on the conductive layer and then a patterned photoresist is formed on the patterned hard mask and the conductive layer. A local metal catalyst layer is formed on the conductive layer in the openings of the patterned photoresist. Carbon nanotubes (CNTs) are grown from the local metal catalyst layer. The conductive layer is etched by using the CNTs and the patterned hard mask as etching mask to form metal features. An inter-level dielectric (ILD) layer is deposited between metal features.

摘要翻译： 公开了制造半导体集成电路（IC）的方法。 该方法包括提供基板。 导电层沉积在衬底上。 在导电层上形成图案化的硬掩模，然后在图案化的硬掩模和导电层上形成图案化的光致抗蚀剂。 在图案化光致抗蚀剂的开口中的导电层上形成局部金属催化剂层。 碳纳米管（CNT）从局部金属催化剂层生长。 通过使用CNT和图案化的硬掩模作为蚀刻掩模来蚀刻导电层以形成金属特征。 在金属特征之间沉积层间电介质（ILD）层。

公开(公告)号：US09947583B2

公开(公告)日：2018-04-17

申请号：US15430852

申请日：2017-02-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Fu Yeh ,  Chao-Hsien Peng ,  Hsien-Chang Wu ,  Hsiang-Huan Lee

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/02

CPC分类号： H01L21/76892 ,  B82Y40/00 ,  H01L21/02115 ,  H01L21/02697 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  H01L2924/00

摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

公开(公告)号：US20170170066A1

公开(公告)日：2017-06-15

申请号：US15430852

申请日：2017-02-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Fu Yeh ,  Chao-Hsien Peng ,  Hsien-Chang Wu ,  Hsiang-Huan Lee

IPC分类号： H01L21/768 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3213

CPC分类号： H01L21/76892 ,  B82Y40/00 ,  H01L21/02115 ,  H01L21/02697 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  H01L2924/00

摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

公开(公告)号：US20170125290A1

公开(公告)日：2017-05-04

申请号：US15407145

申请日：2017-01-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiang-Huan Lee ,  Shau-Lin Shue ,  Kuang-Kuo Koai ,  Hai-Ching Chen ,  Tung-Ching Tseng ,  Wen-Cheng Yang ,  Chung-En Kao ,  Ming-Han Lee ,  Hsin-Yen Huang

IPC分类号： H01L21/768 ,  H01L21/285 ,  H01L21/02 ,  H01L21/67 ,  H01L21/321 ,  H01L21/677

CPC分类号： H01L21/677 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/02063 ,  H01L21/02631 ,  H01L21/2855 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/3212 ,  H01L21/67184 ,  H01L21/67207 ,  H01L21/67742 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76871 ,  H01L21/76877

摘要： Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.

公开(公告)号：US09613854B2

公开(公告)日：2017-04-04

申请号：US14853104

申请日：2015-09-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Yi Yang ,  Hsiang-Huan Lee ,  Ming-Han Lee ,  Ching-Fu Yeh ,  Pei-Yin Liou

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76847 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53276 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a device may include: forming an opening through a dielectric layer and an underlying etching stop layer to expose a metal line. The method may further include the step of catalytically growing a graphene layer on an exposed surface of the metal line, and depositing an amorphous carbon layer on sidewalls of the opening. The steps of catalytically growing the graphene layer and depositing the amorphous carbon layer may be performed simultaneously.

公开(公告)号：US09570347B2

公开(公告)日：2017-02-14

申请号：US14733487

申请日：2015-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Fu Yeh ,  Chao-Hsien Peng ,  Hsien-Chang Wu ,  Hsiang-Huan Lee

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L21/027 ,  H01L21/3213 ,  B82Y40/00

CPC分类号： H01L21/76892 ,  B82Y40/00 ,  H01L21/02115 ,  H01L21/02697 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  H01L2924/00

摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

摘要翻译： 公开了制造半导体集成电路（IC）的方法。 该方法包括提供衬底并在衬底上沉积导电层。 在导电层上形成图案化的硬掩模和催化剂层。 该方法还包括从催化剂层生长多个碳纳米管（CNT）并通过使用CNT和图案化的硬掩模作为蚀刻掩模来蚀刻导电层以形成金属特征。

公开(公告)号：US09466525B2

公开(公告)日：2016-10-11

申请号：US14685217

申请日：2015-04-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-Hsien Peng ,  Hsin-Yen Huang ,  Hsiang-Huan Lee ,  Shau-Lin Shue

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L23/522

CPC分类号： H01L21/76843 ,  H01L21/02118 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure includes a substrate, a low-k dielectric layer over the substrate, and a conductive barrier layer extending into the low-k dielectric layer. The conductive barrier layer includes a sidewall portion. A metal line in the low-k dielectric layer adjoins the conductive barrier layer. An organic buffer layer is between the sidewall portion of the conductive barrier layer and the low-k dielectric layer.

公开(公告)号：US20160240434A1

公开(公告)日：2016-08-18

申请号：US15138033

申请日：2016-04-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Yi Yang ,  Ching-Fu Yeh ,  Tz-Jun Kuo ,  Hsiang-Huan Lee ,  Ming-Han Lee

IPC分类号： H01L21/768

CPC分类号： H01L21/76873 ,  C25D3/38 ,  C25D7/123 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/44 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879

摘要： Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.

公开(公告)号：US09385029B2

公开(公告)日：2016-07-05

申请号：US14570920

申请日：2014-12-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-Hsien Peng ,  Hsiang-Huan Lee ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC分类号： H01L21/76829 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76838 ,  H01L21/76867 ,  H01L21/76868 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. An oxygen-rich layer is formed over the dielectric material layer. The dielectric material layer and the oxygen-rich layer are patterned to form a plurality of vias in the semiconductor substrate. A barrier layer is formed in the plurality of vias and on the dielectric material layer leaving a portion of the oxygen-rich layer exposed. A metal layer is formed on the bather layer and on the exposed portion of the oxygen-rich layer, wherein the metal layer fills the plurality of vias. The semiconductor substrate is annealed at a predetermined temperature range and at a predetermined pressure to transform the exposed portion of the oxygen-rich layer into a metal-oxide stop layer.

摘要翻译： 形成互连结构的方法包括在半导体衬底上形成电介质材料层。 在介电材料层上形成富氧层。 图案化电介质材料层和富氧层，以在半导体衬底中形成多个通孔。 在多个通孔和电介质材料层上形成阻挡层，留下一部分富氧层露出。 在沐浴层和富氧层的暴露部分上形成金属层，其中金属层填充多个通孔。 将半导体衬底在预定温度范围内和预定压力下退火，以将富氧层的暴露部分转变为金属氧化物停止层。

公开(公告)号：US09318364B2

公开(公告)日：2016-04-19

申请号：US14153738

申请日：2014-01-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiang-Huan Lee ,  Shau-Lin Shue ,  Keith Kuang-Kuo Koai ,  Hai-Ching Chen ,  Tung-Ching Tseng ,  Wen-Cheng Yang ,  Chung-En Kao ,  Ming-Han Lee ,  Hsin-Yen Huang

IPC分类号： H01L21/31 ,  H01L21/677 ,  H01L21/02 ,  H01L21/306 ,  H01L21/768 ,  H01L21/67

CPC分类号： H01L21/76846 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/02063 ,  H01L21/02631 ,  H01L21/2855 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/3212 ,  H01L21/67184 ,  H01L21/67207 ,  H01L21/677 ,  H01L21/67742 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/7684 ,  H01L21/76862 ,  H01L21/76871 ,  H01L21/76877

摘要： Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.

摘要翻译： 公开了半导体器件金属化系统和方法。 在一些实施例中，用于半导体器件的金属化系统包括主机以及靠近主机设置的多个模块。 多个模块中的一个模块包括物理气相沉积（PVD）模块，并且多个模块中的一个模块包括紫外线（UV）固化模块。