公开(公告)号：US11581399B2

公开(公告)日：2023-02-14

申请号：US16917293

申请日：2020-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar

IPC: H01L27/07 ,  H01L49/02 ,  H01L21/8238

Abstract: Methods and semiconductor circuits are described in which a polysilicon resistor body is formed over a semiconductor substrate. A first dopant species is implanted into the polysilicon resistor body at a first angle about parallel to a surface normal of a topmost surface of the polysilicon resistor body. A second dopant species is implanted into the polysilicon resistor body at a second angle greater than about 10° relative to the surface normal. The combination of implants reduces the different between the temperature coefficient (tempco) of resistance of narrow resistors relative to the tempco of wide resistors, and brings the tempco of the resistors closer to a preferred value of zero.

公开(公告)号：US11455452B2

公开(公告)日：2022-09-27

申请号：US16944890

申请日：2020-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar ,  Murlidhar Bashyam ,  Alwin Tsao ,  Douglas Newman

IPC: G06F30/30 ,  G06F30/367 ,  H01L21/66 ,  G06F30/398 ,  G06F30/392 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  G06F30/373

Abstract: The present disclosure provides a method for adjusting implant parameter conditions in semiconductor processing by wafer and by wafer zone using in-line measurements from previous operations and a feed-forward computer model. The feed-forward model is based on a sensitivity map of in-line measured data and its effect of electrical performance. Feed-forward computer models that adjust implant parameters by wafer and by zone improve both wafer-to-wafer and within wafer electrical uniformity in semiconductor devices.

公开(公告)号：US11152350B2

公开(公告)日：2021-10-19

申请号：US16220793

申请日：2018-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahalingam Nandakumar ,  Alan Erik Segervall ,  Muhammad Yusuf Ali

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/06 ,  H01L27/08 ,  H01L27/092 ,  H01L21/266

Abstract: An electronic device, e.g. integrated circuit, has an n-type region and a p-type region located within a semiconductor substrate, the n-type region and the p-type region each intersecting the substrate surface. A dielectric structure is located directly on the substrate surface. The dielectric structure has first and second laterally opposed sides, with the first side located over the n-type region and the second side located over the p-type region.

公开(公告)号：US10439041B2

公开(公告)日：2019-10-08

申请号：US15686449

申请日：2017-08-25

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Mahalingam Nandakumar

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/321 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/32

Abstract: A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench.

公开(公告)号：US20180090503A1

公开(公告)日：2018-03-29

申请号：US15826923

申请日：2017-11-30

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L27/11 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8249 ,  H01L29/06 ,  H01L27/092 ,  H01L27/082 ,  H01L27/06

CPC classification number: H01L27/1104 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L27/092 ,  H01L27/1116 ,  H01L29/0638 ,  H01L29/1083 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7802 ,  H01L29/7833

Abstract: An integrated circuit contains a logic MOS transistor and a memory MOS transistor of a same polarity. The logic MOS transistor has a logic channel stop layer. The memory MOS transistor has a memory channel stop layer. An average dopant density of the memory channel stop layer is higher than an average dopant density of the logic channel stop layer. The integrated circuit is formed by forming a global mask which exposes both the logic and memory MOS transistors. A global channel stop dose of dopants is implanted in the logic and memory MOS transistors. A memory mask is formed which exposes the memory MOS transistor and covers the logic MOS transistor. A memory channel stop dose of dopants of the same polarity is implanted into the memory MOS transistors. The memory channel stop dose of dopants is blocked from the logic MOS transistors.

公开(公告)号：US20160300836A1

公开(公告)日：2016-10-13

申请号：US15184405

申请日：2016-06-16

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Mahalingam Nandakumar

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.

公开(公告)号：US09397100B2

公开(公告)日：2016-07-19

申请号：US14578732

申请日：2014-12-22

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Mahalingam Nandakumar

IPC: H01L21/02 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L27/092 ,  H01L21/3213

CPC classification number: H01L27/092 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.

Abstract translation: 一种具有金属栅极NMOS晶体管的集成电路和方法，其在高质量热生长界面电介质上具有高k第一栅极电介质，并且具有在化学生长界面电介质上具有高k最后栅极电介质的金属栅极PMOS晶体管。

公开(公告)号：US09337297B2

公开(公告)日：2016-05-10

申请号：US14578722

申请日：2014-12-22

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Mahalingam Nandakumar

IPC: H01L29/51 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/321 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/7833

Abstract: A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench.

Abstract translation: 替代金属栅极晶体管结构和方法，其具有薄的氮化硅侧壁，并且在替换栅极晶体管沟槽的垂直侧壁上具有很少或不具有高k电介质。

公开(公告)号：US09275988B2

公开(公告)日：2016-03-01

申请号：US14576813

申请日：2014-12-19

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar

IPC: H01L27/06 ,  H01L29/872 ,  H01L29/49 ,  H01L29/47 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L29/36 ,  H01L29/47 ,  H01L29/4966 ,  H01L29/66143 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/872

Abstract: An integrated circuit and method with a metal gate transistor and with a Schottky diode where the metal used to form the Schottky diode is the metal used to form the metal gate.

Abstract translation: 具有金属栅极晶体管和肖特基二极管的集成电路和方法，其中用于形成肖特基二极管的金属是用于形成金属栅极的金属。

公开(公告)号：US08941181B2

公开(公告)日：2015-01-27

申请号：US13710103

申请日：2012-12-10

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Sunitha Venkataraman ,  David L. Catlett, Jr.

IPC: H01L27/08 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092

CPC classification number: H01L27/0255 ,  H01L27/0629 ,  H01L27/0811 ,  H01L27/0814 ,  H01L27/0928 ,  H01L29/0649

Abstract: An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode.

Abstract translation: 具有浅沟槽隔离，低电容，ESD保护二极管的集成电路。 集成电路具有隔离栅极空间，低电容，ESD保护二极管。 集成电路具有隔离的栅极空间，低电容，ESD保护二极管与浅沟槽隔离，低电容，ESD保护二极管。