公开(公告)号：US11949001B2

公开(公告)日：2024-04-02

申请号：US17699362

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Chung-I Yang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/785 ,  H01L2029/7858

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members disposed over a substrate, a gate structure engaging the channel members, and an epitaxial feature adjacent the channel members. At least one of the channel members has an end portion in physical contact with an outer portion of the epitaxial feature. The end portion of the at least one of the channel members includes a first dopant of a first concentration. The outer portion of the epitaxial feature includes a second dopant of a second concentration. The first concentration is higher than the second concentration.

公开(公告)号：US20230145953A1

公开(公告)日：2023-05-11

申请号：US17589500

申请日：2022-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-An Liu ,  Wen-Chiung Tu ,  Yuan-Yang Hsiao ,  Kai Tak Lam ,  Chen-Chiu Huang ,  Zhiqiang Wu ,  Dian-Hau Chen

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/35121

Abstract: Methods and semiconductor structures are provided. A semiconductor structure according to the present disclosure includes a plurality of transistors, an interconnect structure electrically coupled to the plurality of transistors, a metal feature disposed over the interconnect structure and electrically isolated from the plurality of transistors, an insulation layer disposed over the metal feature, and a first redistribution feature and a second redistribution feature disposed over the insulation layer. A space between the first redistribution feature and the second redistribution feature is disposed directly over at least a portion of the metal feature.

公开(公告)号：US20220359731A1

公开(公告)日：2022-11-10

申请号：US17870292

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes channel members vertically stacked over a substrate, a gate structure engaging the channel members, a gate spacer layer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, an inner spacer layer interposing the gate structure and the epitaxial feature, and a semiconductor layer interposing the inner spacer layer and the epitaxial feature.

公开(公告)号：US20220208989A1

公开(公告)日：2022-06-30

申请号：US17699362

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Chung-I Yang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/417

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members disposed over a substrate, a gate structure engaging the channel members, and an epitaxial feature adjacent the channel members. At least one of the channel members has an end portion in physical contact with an outer portion of the epitaxial feature. The end portion of the at least one of the channel members includes a first dopant of a first concentration. The outer portion of the epitaxial feature includes a second dopant of a second concentration. The first concentration is higher than the second concentration.

公开(公告)号：US11342016B2

公开(公告)日：2022-05-24

申请号：US17110624

申请日：2020-12-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gaurav Gupta ,  Zhiqiang Wu

IPC: G11C11/00 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a first read bias transistor, a first pull-up read-enable transistor, an MTJ memory cell, a first pull-down read-enable transistor, and a first non-linear resistance device. The first non-linear resistance device is coupled in series and between the first pull-up read-enable transistor and the first read bias transistor. The first non-linear resistance device is configured to provide a first resistance when applied a first voltage and a second resistance greater than the first resistance when applied a second voltage smaller than the first voltage.

公开(公告)号：US11145762B2

公开(公告)日：2021-10-12

申请号：US16016748

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng Wei ,  Hung-Li Chiang ,  Chia-Wen Liu ,  Yi-Ming Sheu ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ying-Keung Leung

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

公开(公告)号：US10707349B2

公开(公告)日：2020-07-07

申请号：US16376563

申请日：2019-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Ka-Hing Fung ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66

Abstract: A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors.

公开(公告)号：US20190386061A1

公开(公告)日：2019-12-19

申请号：US16379901

申请日：2019-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-An Liu ,  Chung-Cheng Wu ,  Harry-Hak-Lay Chuang ,  Gwan-Sin Chang ,  Tien-Wei Chiang ,  Zhiqiang Wu ,  Chia-Hsiang Chen

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a chip that includes a magnetic random access memory (MRAM) cell. A magnetic-field-shielding structure comprised of conductive or magnetic material at least partially surrounds the chip. The magnetic-field-shielding structure comprises a sidewall region that laterally surrounds the chip, an upper region extending upward from the sidewall region, and a lower region extending downward from the sidewall region. At least one of the upper region and/or lower region terminate at an opening over the chip.

公开(公告)号：US10276717B2

公开(公告)日：2019-04-30

申请号：US15247024

申请日：2016-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tzer-Min Shen ,  Chun-Fu Cheng ,  Hong-Shen Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L21/265

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.

公开(公告)号：US10134915B2

公开(公告)日：2018-11-20

申请号：US15615498

申请日：2017-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre Colinge ,  Chung-Cheng Wu ,  Carlos H. Diaz ,  Chih-Hao Wang ,  Ken-Ichi Goto ,  Ta-Pen Guo ,  Yee-Chia Yeo ,  Zhiqiang Wu ,  Yu-Ming Lin

IPC: H01L21/02 ,  H01L29/786 ,  H01L27/088 ,  H01L29/16 ,  H01L29/24 ,  H01L21/8256 ,  H01L21/8238 ,  H01L29/78

Abstract: Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.