公开(公告)号：US09159798B2

公开(公告)日：2015-10-13

申请号：US13886382

申请日：2013-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Cheng-Guo Chen ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chung-Fu Chang

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7851

Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.

Abstract translation: 公开了替代浇口工艺。 提供了一种在基板上形成的基板和虚拟栅极结构，其中，虚设栅极结构包括基板上的虚设层，虚设层上的硬掩模层，虚设层两侧的间隔物和硬掩模层， 以及覆盖衬底，间隔物和硬掩模层的接触蚀刻停止层（CESL）。 垫片和CESL由相同的材料制成。 然后，去除CESL的顶部以露出硬掩模层。 接下来，去除硬掩模层。 之后，去除虚拟层以形成沟槽。

公开(公告)号：US20150118835A1

公开(公告)日：2015-04-30

申请号：US14062909

申请日：2013-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Chien-Ting Lin

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized.

Abstract translation: 一种制造半导体器件的方法包括以下步骤。 提供了至少具有嵌入在其上形成绝缘材料的晶体管的衬底。 晶体管包括金属栅极。 接下来，进行蚀刻处理以去除金属栅极的一部分以形成凹部并且去除绝缘材料的一部分以形成锥形部分。 在形成凹部和绝缘材料的锥形部分之后，在基板上形成硬掩模层以填充凹部。 随后，硬掩模层被平坦化。

公开(公告)号：US09006091B2

公开(公告)日：2015-04-14

申请号：US14302047

申请日：2014-06-11

Applicant: United Microelectronics Corp.

Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Chien-Ting Lin ,  Wen-Tai Chiang

IPC: H01L21/338 ,  H01L29/66 ,  H01L21/283 ,  H01L21/28 ,  H01L21/762 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/6681 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/283 ,  H01L21/76224 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.

Abstract translation: 提供一种形成半导体器件的方法。 通过在衬底上的沉积工艺形成第一界面材料层。 在第一界面材料层上形成虚拟栅极材料层。 将虚拟栅材料层和第一界面材料层图案化以形成堆叠结构。 形成层间电介质（ILD）层以覆盖层叠结构。 去除ILD层的一部分以露出堆叠结构的顶部。 去除层叠结构以在ILD层中形成沟槽。 至少在沟槽的表面上共形地形成第二界面层和第一高k层。 复合金属层形成为至少填充沟槽。

公开(公告)号：US20150017781A1

公开(公告)日：2015-01-15

申请号：US13941208

申请日：2013-07-12

Applicant: United Microelectronics Corp.

Inventor： Chien-Ting Lin ,  Shih-Hung Tsai ,  Chun-Hsien Lin

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845

Abstract: A method of forming a shallow trench isolation structure is disclosed. Hard mask patterns are formed on a substrate. A portion of the substrate is removed, using the hard mask patterns as a mask, to form first trenches in the substrate, wherein a fin is disposed between the neighboring first trenches. A filling layer is formed in the first trenches. A patterned mask layer is formed on the filling layer. A portion of the filling layer and a portion of the fins are removed, using the patterned mask layer as a mask, to form second trenches in the substrate. A first insulating layer is formed on the substrate filling in the second trenches.

Abstract translation: 公开了形成浅沟槽隔离结构的方法。 在基板上形成硬掩模图案。 使用硬掩模图案作为掩模去除衬底的一部分，以在衬底中形成第一沟槽，其中翅片设置在相邻的第一沟槽之间。 在第一沟槽中形成填充层。 在填充层上形成图案化掩模层。 使用图案化掩模层作为掩模，去除填充层的一部分和散热片的一部分，以在衬底中形成第二沟槽。 在填充在第二沟槽中的衬底上形成第一绝缘层。

公开(公告)号：US20140361373A1

公开(公告)日：2014-12-11

申请号：US13913511

申请日：2013-06-09

Applicant: United Microelectronics Corp.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chung-Fu Chang ,  Cheng-Guo Chen ,  Chien-Ting Lin

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/8234 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7855

Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface and the isolation structure at two sides of the gate structure has a second top surface, wherein the first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.

Abstract translation: 半导体器件包括鳍结构，隔离结构，栅极结构和外延结构。 翅片结构从衬底的表面突出并且包括顶表面和两个侧壁。 隔离结构围绕翅片结构。 栅极结构覆盖鳍结构的一部分的顶表面和两个侧壁，并且覆盖隔离结构的一部分。 栅极结构下的隔离结构具有第一顶表面，并且栅极结构两侧的隔离结构具有第二顶表面，其中第一顶表面高于第二顶表面。 外延层设置在栅极结构的一侧并与鳍结构直接接触。

公开(公告)号：US08895396B1

公开(公告)日：2014-11-25

申请号：US13940220

申请日：2013-07-11

Applicant: United Microelectronics Corp.

Inventor： Ssu-I Fu ,  Yu-Hsiang Hung ,  Cheng-Guo Chen ,  Chung-Fu Chang ,  Chien-Ting Lin

IPC: H01L21/8236 ,  H01L21/8234

CPC classification number: H01L21/823418 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: An epitaxial process includes the following steps. A first gate and a second gate are formed on a substrate. Two first spacers are formed on the substrate beside the first gate and the second gate respectively. Two first epitaxial layers having first profiles are formed in the substrate beside the two first spacers respectively. A second spacer material is formed to cover the first gate and the second gate. The second spacer material covering the second gate is etched to form a second spacer on the substrate beside the second gate and expose the first epitaxial layer beside the second spacer while reserving the second spacer material covering the first gate. The exposed first epitaxial layer in the substrate beside the second spacer is replaced by a second epitaxial layer having a second profile different from the first profile.

Abstract translation: 外延工艺包括以下步骤。 在基板上形成第一栅极和第二栅极。 分别在第一栅极和第二栅极旁边的基板上形成两个第一间隔物。 分别在两个第一间隔物旁边的衬底中形成具有第一轮廓的两个第一外延层。 形成第二间隔材料以覆盖第一栅极和第二栅极。 蚀刻覆盖第二栅极的第二间隔物材料，以在第二栅极旁边的衬底上形成第二间隔物，并在第二间隔物旁边露出第一外延层，同时保留覆盖第一栅极的第二间隔物材料。 在第二间隔物旁边的衬底中的暴露的第一外延层由具有不同于第一轮廓的第二轮廓的第二外延层代替。

公开(公告)号：US08841197B1

公开(公告)日：2014-09-23

申请号：US13786485

申请日：2013-03-06

Applicant: United Microelectronics Corp.

Inventor： Shih-Hung Tsai ,  Chun-Hsien Lin ,  Chien-Ting Lin

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/461 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/31053 ,  H01L21/76229 ,  H01L29/66795

Abstract: The present invention provides a method for forming a fin structure comprising the following steps: first, a multiple-layer structure is formed on a substrate; then, a sacrificial pattern is formed on the multiple-layer structure, a spacer is formed on the sidewall of the sacrificial pattern and disposed on the multiple-layer structure, the sacrificial pattern is removed, the spacer is used as a cap layer to etch parts of the multiple-layer structure, and then the multiple-layer structure is used as a cap layer to etch the substrate and to form at least one fin structure in the substrate.

Abstract translation: 本发明提供一种形成翅片结构的方法，包括以下步骤：首先，在基板上形成多层结构; 那么，在多层结构上形成牺牲图案，在牺牲图案的侧壁上形成隔离物并且设置在多层结构上，去除牺牲图案，将间隔物用作盖层以蚀刻 多层结构的部分，然后多层结构用作覆盖层以蚀刻基底并在基底中形成至少一个翅片结构。

公开(公告)号：US20140103443A1

公开(公告)日：2014-04-17

申请号：US14135588

申请日：2013-12-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

Abstract: A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench.

Abstract translation: 具有金属栅极的半导体器件包括具有形成在其上的第一栅极沟槽和第二栅极沟槽的衬底，分别形成在第一栅极沟槽和第二栅极沟槽中的栅极电介质层，形成在栅极上的第一功函数金属层 第一栅极沟槽和第二栅极沟槽中的介电层，分别形成在第一栅极沟槽和第二栅极沟槽中的第二功函数金属层和形成在第二功函数金属层上的填充金属层。 第二栅极沟槽的开口宽度大于第一栅极沟槽的开口宽度。 第一栅极沟槽中的第二功函数金属层的上部区域比第一栅极沟槽中的第二功函数金属层的下部区域宽。

公开(公告)号：US20140057403A1

公开(公告)日：2014-02-27

申请号：US14069179

申请日：2013-10-31

Applicant: United Microelectronics Corp.

Inventor： Chang-Tzu Wang ,  Mei-Ling Chao ,  Chien-Ting Lin

IPC: H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/823821 ,  H01L27/0924

Abstract: A method for fabricating a semiconductor device is provided. A fin of a first conductivity type is formed on a substrate of the first conductivity type. A gate is formed on the substrate, wherein the gate covers a portion of the fin. Source and drain regions of a second conductivity type are formed in the fin at respective sides of the gate. A punch-through stopper (PTS) of the first conductivity type is formed in the fin underlying the gate and between the source and drain regions, wherein the PTS has an impurity concentration higher than that of the substrate. A first impurity of the second conductivity type is implanted into the PTS, so as to compensate the impurity concentration of the PTS.

Abstract translation: 提供一种制造半导体器件的方法。 在第一导电类型的衬底上形成第一导电类型的鳍。 栅极形成在衬底上，其中栅极覆盖鳍片的一部分。 第二导电类型的源极和漏极区域形成在栅极的相应侧的翅片中。 第一导电类型的穿通止动件（PTS）形成在栅极下方的栅极和源极和漏极区域之间，其中PTS的杂质浓度高于衬底的杂质浓度。 将第二导电类型的第一杂质注入到PTS中，以补偿PTS的杂质浓度。

公开(公告)号：US12261086B2

公开(公告)日：2025-03-25

申请号：US17586699

申请日：2022-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Chien-Ting Lin ,  Chun-Ya Chiu ,  Chia-Jung Hsu ,  Chin-Hung Chen

IPC: H01L21/8234 ,  H01L23/60 ,  H01L27/088

Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.