公开(公告)号：US09583394B2

公开(公告)日：2017-02-28

申请号：US15293292

申请日：2016-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Hon-Huei Liu ,  Chao-Hung Lin ,  Nan-Yuan Huang ,  Jyh-Shyang Jenq

IPC: H01L21/324 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/308 ,  H01L27/092 ,  H01L21/306 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/7842 ,  H01L29/785

Abstract: The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, having a first fin structure and a second fin structure disposed thereon, next, a first isolation region is formed between the first fin structure and the second fin structure, a second isolation region is formed opposite the first fin structure from the first isolation region, and at least an epitaxial layer is formed on the side of the first fin structure and the second fin structure, wherein the epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region, in addition, the epitaxial layer has a stepped-shaped sidewall profile.

Abstract translation: 本发明提供一种半导体结构的形成方法，其特征在于，首先，设置具有第一鳍结构和设置在其上的第二鳍结构的衬底，接着，在所述第一鳍结构和所述第二鳍结构之间形成第一隔离区 鳍结构，与第一隔离区相对地形成第二隔离区，并且在第一鳍结构和第二鳍结构的一侧形成至少外延层，其中外延层具有底表面 所述底表面从所述第一鳍结构延伸到所述第二鳍结构，并且所述底表面低于所述第一隔离区域的底表面和所述第二隔离区域的顶表面，此外，所述外延层具有阶梯状 形侧壁轮廓。

公开(公告)号：US20170005102A1

公开(公告)日：2017-01-05

申请号：US14816081

申请日：2015-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Shih-Fang Hong ,  Jyh-Shyang Jenq

IPC: H01L27/11 ,  H01L21/8238 ,  H01L21/762 ,  H01L27/092

CPC classification number: H01L21/76229 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a plurality of spacers on the first region, the second region, and the third region; forming a first patterned mask to cover the spacers on the first region and the second region; and removing the spacers on the third region.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有第一区域，第二区域和第三区域的衬底; 在所述第一区域，所述第二区域和所述第三区域上形成多个间隔物; 形成第一图案化掩模以覆盖第一区域和第二区域上的间隔物; 并移除第三区域上的间隔物。

公开(公告)号：US09484263B1

公开(公告)日：2016-11-01

申请号：US14926003

申请日：2015-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Jyh-Shyang Jenq ,  Ching-Ling Lin ,  Yi-Wen Chen ,  Chen-Ming Huang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L21/823437 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823468 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method of removing a hard mask on a gate includes forming a first gate structure and a second gate structure. The first gate structure includes a first gate, a first hard mask disposed on the first gate and a first spacer surrounding the first gate and the first hard mask, wherein the second gate structure includes a second gate, a second hard mask disposed on the second gate and a second spacer surrounding the second gate and the second hard mask. Later, the first spacer surrounding the first hard mask and the second spacer surrounding the second hard mask are removed. After that, a dielectric layer is formed to cover the first hard mask and the second hard mask. Finally, the second dielectric layer, the first mask layer and the second mask layer are removed.

Abstract translation: 去除栅极上的硬掩模的方法包括形成第一栅极结构和第二栅极结构。 第一栅极结构包括第一栅极，设置在第一栅极上的第一硬掩模和围绕第一栅极和第一硬掩模的第一隔离物，其中第二栅极结构包括第二栅极，设置在第二栅极上的第二硬掩模 栅极和围绕第二栅极和第二硬掩模的第二隔板。 随后，围绕第一硬掩模的第一间隔物和围绕第二硬掩模的第二间隔物被去除。 之后，形成介电层以覆盖第一硬掩模和第二硬掩模。 最后，去除第二电介质层，第一掩模层和第二掩模层。

公开(公告)号：US20160218179A1

公开(公告)日：2016-07-28

申请号：US14634904

申请日：2015-03-02

Applicant: United Microelectronics Corp.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Shih-Fang Hong ,  Chao-Hung Lin ,  Jyh-Shyang Jenq

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L21/02603 ,  H01L21/823807 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

Abstract: A nanowire transistor device includes a substrate, a plurality of nanowires formed on the substrate, and a gate surrounding at least a portion of each nanowire. The nanowires respectively include a first semiconductor core and a second semiconductor core surrounding the first semiconductor core. A lattice constant of the second semiconductor core is different from a lattice constant of the first semiconductor core.

Abstract translation: 纳米线晶体管器件包括衬底，形成在衬底上的多个纳米线和围绕每个纳米线的至少一部分的栅极。 纳米线分别包括第一半导体芯和围绕第一半导体芯的第二半导体芯。 第二半导体芯的晶格常数与第一半导体芯的晶格常数不同。

公开(公告)号：US20160190287A1

公开(公告)日：2016-06-30

申请号：US14607085

申请日：2015-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Chao-Hung Lin ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Shih-Hung Tsai ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/3105

CPC classification number: H01L29/66795 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/665 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes following steps. Firstly, a substrate having a transistor is provided, where the transistor includes a source/drain region. A dielectric layer is formed on the substrate, and a contact plug is formed in the dielectric layer to electrically connect the source/drain region. Next, a mask layer is formed on the dielectric layer, where the mask layer includes a first layer and a second layer stacked thereon. After this a slot-cut pattern is formed on the second layer of the mask layer, and a contact slot pattern is formed on the first layer of the mask layer. Finally, the second layer is removed and a contact opening is formed by using the contact slot pattern on the first layer.

Abstract translation: 形成半导体器件的方法包括以下步骤。 首先，提供具有晶体管的衬底，其中晶体管包括源极/漏极区域。 在基板上形成电介质层，并且在电介质层中形成接触插塞以电连接源极/漏极区域。 接下来，在电介质层上形成掩模层，其中掩模层包括第一层和堆叠在其上的第二层。 之后，在掩模层的第二层上形成槽切割图案，并且在掩模层的第一层上形成接触槽图案。 最后，通过使用第一层上的接触槽图案，去除第二层并形成接触开口。

公开(公告)号：US09349653B2

公开(公告)日：2016-05-24

申请号：US14539225

申请日：2014-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Chih-Sen Huang ,  Li-Wei Feng ,  Jyh-Shyang Jenq

IPC: H01L21/8228 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/76847 ,  H01L21/76897 ,  H01L21/823431 ,  H01L29/66795

Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method includes the following steps. A substrate is provided. A fin structure and an inter-layer dielectric layer are formed on the substrate. A plurality of gate structures is formed on the substrate. A cap layer is formed on the gate structures. A hard mask is formed on the cap layer. A first patterned photoresist layer covering the gate structures is formed on the hard mask. The hard mask is etched and patterned to form a patterned hard mask, such that the patterned hard mask covers the gate structures. A second patterned photoresist layer including a plurality of openings corresponding to the fin structure is formed on the patterned hard mask. The cap layer and the inter-layer dielectric layer are etched to form a plurality of first trenches exposing part of the fin structure.

Abstract translation: 提供一种半导体结构的制造方法。 该制造方法包括以下步骤。 提供基板。 在基板上形成翅片结构和层间电介质层。 在基板上形成多个栅极结构。 在栅极结构上形成盖层。 在盖层上形成硬掩模。 在硬掩模上形成覆盖栅极结构的第一图案化光致抗蚀剂层。 硬掩模被蚀刻和图案化以形成图案化的硬掩模，使得图案化的硬掩模覆盖栅极结构。 在图案化的硬掩模上形成包括对应于鳍结构的多个开口的第二图案化光致抗蚀剂层。 蚀刻覆盖层和层间电介质层以形成暴露鳍结构的一部分的多个第一沟槽。

公开(公告)号：US09076870B2

公开(公告)日：2015-07-07

申请号：US13772343

申请日：2013-02-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ting Lin ,  Shih-Hung Tsai

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/66795

Abstract: A method for forming a fin-shaped structure includes the following steps. A pad layer is formed on a substrate. A sacrificial pattern is formed on the pad layer. A spacer is formed on the pad layer beside the sacrificial pattern, wherein the ratio of the height of the spacer to the pad layer is larger than 5. The sacrificial pattern is removed. The layout of the spacer is transferred to the substrate to form at least a fin-shaped structure having a taper profile in the substrate.

Abstract translation: 形成翅片状结构的方法包括以下步骤。 衬底层形成在衬底上。 牺牲图案形成在衬垫层上。 在牺牲图案旁边的垫层上形成间隔物，其中间隔物与垫层的高度比大于5.牺牲图案被去除。 间隔物的布局被转移到基底以至少形成在基底中具有锥形轮廓的鳍状结构。

公开(公告)号：US20150064929A1

公开(公告)日：2015-03-05

申请号：US14018447

申请日：2013-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Shih-Hung Tsai ,  Rai-Min Huang ,  Yu-Ting Lin ,  Chien-Ting Lin ,  Shih-Fang Tzou

IPC: H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/76224

Abstract: A method of gap filling includes providing a substrate having a plurality of gaps formed therein. Then, an in-situ steam generation oxidation is performed to form an oxide liner on the substrate. The oxide liner is formed to cover surfaces of the gaps. Subsequently, a high aspect ratio process is performed to form an oxide protecting layer on the oxide liner. After forming the oxide protecting layer, a flowable chemical vapor deposition is performed to form an oxide filling on the oxide protecting layer. More important, the gaps are filled up with the oxide filling layer.

Abstract translation: 间隙填充的方法包括提供其中形成有多个间隙的基板。 然后，进行原位蒸汽发生氧化，以在衬底上形成氧化物衬垫。 形成氧化物衬垫以覆盖间隙的表面。 随后，进行高纵横比处理以在氧化物衬垫上形成氧化物保护层。 在形成氧化物保护层之后，进行可流动的化学气相沉积以在氧化物保护层上形成填充氧化物。 更重要的是，间隙填充有氧化物填充层。

公开(公告)号：US20150014808A1

公开(公告)日：2015-01-15

申请号：US13939204

申请日：2013-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Rai-Min Huang ,  I-Ming Tseng ,  Yu-Ting Lin ,  Chien-Ting Lin

IPC: H01L21/762 ,  H01L21/311 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/02236 ,  H01L21/3065 ,  H01L21/3086 ,  H01L29/66818 ,  H01L29/7853

Abstract: A fabrication method for a semiconductor structure at least includes the following steps. First, a pattern mask with a predetermined layout pattern is formed on a substrate. The layout pattern is then transferred to the underneath substrate so as to form at least a fin-shaped structure in the substrate. Subsequently, a shallow trench isolation structure is formed around the fin-shaped structure. Afterwards, a steam oxidation process is carried out to oxidize the fin-shaped structure protruding from the shallow trench isolation and to form an oxide layer on its surface. Finally, the oxide layer is removed completely.

Abstract translation: 半导体结构的制造方法至少包括以下步骤。 首先，在基板上形成具有预定布局图案的图案掩模。 然后将布局图案转移到基底下方，以在基底中形成至少一个鳍状结构。 随后，在鳍状结构周围形成浅沟槽隔离结构。 之后，进行蒸汽氧化处理，使从浅沟槽隔离突出的鳍状结构氧化，并在其表面形成氧化物层。 最后，氧化层被完全去除。

公开(公告)号：US20140295660A1

公开(公告)日：2014-10-02

申请号：US14302047

申请日：2014-06-11

Applicant: United Microelectronics Corp.

Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Chien-Ting Lin ,  Wen-Tai Chiang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/28

CPC classification number: H01L29/6681 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/283 ,  H01L21/76224 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally foamed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.

Abstract translation: 提供一种形成半导体器件的方法。 通过在衬底上的沉积工艺形成第一界面材料层。 在第一界面材料层上形成虚拟栅极材料层。 将虚拟栅材料层和第一界面材料层图案化以形成堆叠结构。 形成层间电介质（ILD）层以覆盖层叠结构。 去除ILD层的一部分以露出堆叠结构的顶部。 去除层叠结构以在ILD层中形成沟槽。 第二界面层和第一高k层至少在沟槽的表面上保形发泡。 复合金属层形成为至少填充沟槽。