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公开(公告)号：US20130277714A1
公开(公告)日：2013-10-24
申请号：US13977188
申请日：2011-12-09
申请人： Van H. Le , Benjamin Chu-Kung , Harold Hal W. Kennel , Willy Rachmady , Ravi Pillarisetty , Jack T. Kavalieros
发明人： Van H. Le , Benjamin Chu-Kung , Harold Hal W. Kennel , Willy Rachmady , Ravi Pillarisetty , Jack T. Kavalieros
CPC分类号： H01L29/0673 , H01L21/02532 , H01L21/283 , H01L29/0649 , H01L29/0847 , H01L29/1054 , H01L29/155 , H01L29/161 , H01L29/165 , H01L29/42392 , H01L29/66431 , H01L29/66477 , H01L29/66651 , H01L29/66795 , H01L29/78 , H01L29/7842 , H01L29/7849 , H01L29/785 , H01L29/7851 , H01L29/78681 , H01L29/78687 , H01L29/78696
摘要： Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.
摘要翻译： 提供具有包括压缩和拉伸应变外延材料的交替层的沟道区的晶体管结构。 交替的外延层可以在单和多晶体管结构中形成沟道区。 在替代实施例中，两个交替层中的一个被选择性地蚀刻掉以形成剩余材料的纳米带或纳米线。 得到的应变纳米带或纳米线形成晶体管结构的沟道区。 还提供了包括晶体管的计算设备，晶体管包括由交替的压缩和拉伸应变外延层组成的沟道区，以及包括包含由应变纳米带或纳米线组成的沟道区的晶体管的计算器件。
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52.发明授权公开(公告)号：US09653548B2
公开(公告)日：2017-05-16
申请号：US15135262
申请日：2016-04-21
IPC分类号： H01L29/00 , H01L29/06 , H01L29/78 , B82Y10/00 , H01L29/775 , H01L29/205 , H01L29/40 , H01L29/423 , H01L29/51 , H01L29/786 , H01L29/201 , H01L29/66 , B82Y99/00
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y99/00 , H01L29/0665 , H01L29/201 , H01L29/205 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42392 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
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53.发明申请NON-PLANAR SEMICONDUCTOR DEVICE HAVING CHANNEL REGION WITH LOW BAND-GAP CLADDING LAYER 有权具有低带隙封装层的通道区域的非平面半导体器件公开(公告)号：US20140084239A1
公开(公告)日：2014-03-27
申请号：US13629148
申请日：2012-09-27
申请人： Marko Radosavljevic , Gilbert Dewey , Benjamin Chu-Kung , Dipanjan Basu , Sanaz K. Gardner , Satyarth Suri , Ravi Pillarisetty , Niloy Mukherjee , Han Wui Then , Robert S. Chau
发明人： Marko Radosavljevic , Gilbert Dewey , Benjamin Chu-Kung , Dipanjan Basu , Sanaz K. Gardner , Satyarth Suri , Ravi Pillarisetty , Niloy Mukherjee , Han Wui Then , Robert S. Chau
IPC分类号： H01L29/78 , H01L29/267 , H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/068 , H01L29/201 , H01L29/401 , H01L29/42392 , H01L29/66469 , H01L29/775 , H01L29/785 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： Non-planar semiconductor devices having channel regions with low band-gap cladding layers are described. For example, a semiconductor device includes a vertical arrangement of a plurality of nanowires disposed above a substrate. Each nanowire includes an inner region having a first band gap and an outer cladding layer surrounding the inner region. The cladding layer has a second, lower band gap. A gate stack is disposed on and completely surrounds the channel region of each of the nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the nanowires.
摘要翻译： 描述具有低带隙包层的沟道区的非平面半导体器件。 例如，半导体器件包括布置在衬底上方的多个纳米线的垂直布置。 每个纳米线包括具有第一带隙的内部区域和围绕内部区域的外部包层。 包层具有第二较低带隙。 栅堆叠设置在每个纳米线的沟道区上并完全包围。 栅极堆叠包括设置在包层上并围绕着包层的栅极电介质层和设置在栅极介电层上的栅电极。 源区和漏区设置在纳米线的沟道区的两侧。
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公开(公告)号：US20130277683A1
公开(公告)日：2013-10-24
申请号：US13976837
申请日：2011-12-19
申请人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
发明人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
IPC分类号： H01L29/778 , H01L29/66
CPC分类号： H01L29/7787 , G06F1/1633 , G06F1/189 , H01L21/02381 , H01L21/02433 , H01L21/0254 , H01L29/045 , H01L29/0657 , H01L29/0847 , H01L29/1037 , H01L29/2003 , H01L29/205 , H01L29/402 , H01L29/66462 , H01L29/7783 , H01L29/7786 , H01L29/7789 , H01L29/785 , H03F3/195 , H03F3/213 , H03F2200/451
摘要： Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (10 10) plane on a (110) plane of the silicon.
摘要翻译： 用于高压和高频工作的晶体管。 具有设置在第一和第二相对侧壁之间的顶表面的非平面极性结晶半导体本体包括具有设置在第一和第二侧壁上的第一晶体半导体层的沟道区。 第一晶体半导体层是在沟道区内提供二维电子气（2DEG）。 栅极结构沿至少第二侧壁设置在第一晶体半导体层上方，以调制2DEG。 非平面极性结晶半导体主体的第一和第二侧壁可具有不同的极性，其中通道靠近第一侧壁。 栅极结构可以沿着侧壁中的第二侧面以栅极背栅。 极性结晶半导体体可以是在硅衬底上形成的III族氮化物，其中（10 10）面在硅的（110）平面上。
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公开(公告)号：US09245989B2
公开(公告)日：2016-01-26
申请号：US13976414
申请日：2011-12-19
申请人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
发明人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
IPC分类号： H01L29/775 , H01L29/66 , G05F3/02 , H01L29/786 , B82Y10/00 , H01L29/06 , H01L29/20
CPC分类号： H01L29/0673 , B82Y10/00 , G05F3/02 , H01L21/02603 , H01L21/02636 , H01L21/225 , H01L21/283 , H01L21/30604 , H01L21/31 , H01L21/31116 , H01L21/32133 , H01L21/324 , H01L29/04 , H01L29/0676 , H01L29/068 , H01L29/2003 , H01L29/41725 , H01L29/42356 , H01L29/42392 , H01L29/66439 , H01L29/66462 , H01L29/66469 , H01L29/775 , H01L29/78696
摘要： Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, and drain and source contacts similarly coaxially wrap completely around the drain and source regions.
摘要翻译： 晶体管适用于高电压和高频工作。 纳米线垂直或水平地布置在基底上。 纳米线的纵向长度被限定为第一半导体材料的沟道区域，与沟道区域的第一端电耦合的源极区域，与沟道区域的第二端电耦合的漏极区域和外部漏极 区域设置在沟道区域和漏极区域之间。 外在漏极区具有比第一半导体更宽的带隙。 包括栅极导体和栅极绝缘体的栅极堆叠器完全同轴地包裹在沟道区域周围，并且漏极和源极触点类似地同轴地围绕漏极和源极区域包裹。
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56.发明申请NON-PLANAR SEMICONDUCTOR DEVICE HAVING GROUP III-V MATERIAL ACTIVE REGION WITH MULTI-DIELECTRIC GATE STACK 审中-公开具有多层电极堆叠的III-V族材料活性区域的非平面半导体器件公开(公告)号：US20150221762A1
公开(公告)日：2015-08-06
申请号：US14688410
申请日：2015-04-16
IPC分类号： H01L29/78 , H01L29/06 , H01L29/423 , H01L29/201 , H01L29/51
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y99/00 , H01L29/0665 , H01L29/201 , H01L29/205 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42392 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
摘要翻译： 描述具有多电介质栅叠层的具有III-V族材料的区域的非平面半导体器件。 例如，半导体器件包括设置在衬底上的异质结构。 异质结构包括具有沟道区的三维III-V族材料体。 源极和漏极材料区域设置在三维III-V族材料体上方。 在源极和漏极材料区域中布置沟槽，其将源极区域与漏极区域分离，并且暴露沟道区域的至少一部分。 栅极堆叠设置在沟槽中和沟道区域的暴露部分上。 栅极堆叠包括第一和第二电介质层和栅电极。
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公开(公告)号：US20110312140A1
公开(公告)日：2011-12-22
申请号：US13216569
申请日：2011-08-24
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L29/0657 , H01L29/0834 , H01L29/42312 , H01L29/66356 , H01L29/7391
摘要： A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is out of the first plane.
摘要翻译： 微电子器件包括具有第一栅极和第二栅极的P-I-N（p +区域，本征半导体和n +区域）半导体。 第一栅极是设置在上表面平面上的栅极堆叠，并且第二栅极从超出第一平面的第二平面访问半导体本体。
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公开(公告)号：US09461160B2
公开(公告)日：2016-10-04
申请号：US13976837
申请日：2011-12-19
申请人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
发明人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
IPC分类号： H01L29/778 , H01L29/66 , H01L29/78 , H01L29/20
CPC分类号： H01L29/7787 , G06F1/1633 , G06F1/189 , H01L21/02381 , H01L21/02433 , H01L21/0254 , H01L29/045 , H01L29/0657 , H01L29/0847 , H01L29/1037 , H01L29/2003 , H01L29/205 , H01L29/402 , H01L29/66462 , H01L29/7783 , H01L29/7786 , H01L29/7789 , H01L29/785 , H03F3/195 , H03F3/213 , H03F2200/451
摘要： Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (1010) plane on a (110) plane of the silicon.
摘要翻译： 用于高压和高频工作的晶体管。 具有设置在第一和第二相对侧壁之间的顶表面的非平面极性晶体半导体本体包括具有设置在第一和第二侧壁上的第一晶体半导体层的沟道区域。 第一晶体半导体层是在沟道区内提供二维电子气（2DEG）。 栅极结构沿至少第二侧壁设置在第一晶体半导体层上方，以调制2DEG。 非平面极性结晶半导体主体的第一和第二侧壁可具有不同的极性，其中通道靠近第一侧壁。 栅极结构可以沿着侧壁中的第二侧面以栅极背栅。 极性结晶半导体体可以是在硅衬底上形成的III族氮化物，其中（1010）面在硅的（110）平面上。
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59.发明授权Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack 有权具有具有多电介质栅叠层的III-V族材料有源区的非平面半导体器件公开(公告)号：US09343574B2
公开(公告)日：2016-05-17
申请号：US14688410
申请日：2015-04-16
IPC分类号： H01L29/00 , H01L29/78 , B82Y10/00 , H01L29/775 , H01L29/06 , H01L29/205 , H01L29/40 , H01L29/423 , H01L29/51 , H01L29/786 , H01L29/201 , B82Y99/00
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y99/00 , H01L29/0665 , H01L29/201 , H01L29/205 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42392 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
摘要翻译： 描述具有多电介质栅叠层的具有III-V族材料的区域的非平面半导体器件。 例如，半导体器件包括设置在衬底上的异质结构。 异质结构包括具有沟道区的三维III-V族材料体。 源极和漏极材料区域设置在三维III-V族材料体上方。 在源极和漏极材料区域中布置沟槽，其将源极区域与漏极区域分离，并且暴露沟道区域的至少一部分。 栅极堆叠设置在沟槽中和沟道区域的暴露部分上。 栅极堆叠包括第一和第二电介质层和栅电极。
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公开(公告)号：US20150206796A1
公开(公告)日：2015-07-23
申请号：US14162717
申请日：2014-01-23
申请人： Sansaptak Dasgupta , Han Wui Then , Sanaz K. Gardner , Seung Hoon Sung , Marko Radosavljevic , Benjamin Chu-Kung , Sherry R. Taft , Ravi Pillarisetty , Robert S. Chau
发明人： Sansaptak Dasgupta , Han Wui Then , Sanaz K. Gardner , Seung Hoon Sung , Marko Radosavljevic , Benjamin Chu-Kung , Sherry R. Taft , Ravi Pillarisetty , Robert S. Chau
IPC分类号： H01L21/768 , H01L21/762 , H01L21/02
CPC分类号： H01L29/2003 , H01L21/02381 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L21/02647 , H01L21/76229 , H01L21/76232 , H01L21/8258 , H01L29/045 , H01L29/0649 , H01L29/0684
摘要： A trench comprising a portion of a substrate is formed. A nucleation layer is deposited on the portion of the substrate within the trench. A III-N material layer is deposited on the nucleation layer. The III-N material layer is laterally grown over the trench. A device layer is deposited on the laterally grown III-N material layer. A low defect density region is obtained on the laterally grown material and is used for electronic device fabrication of III-N materials on Si substrates.
摘要翻译： 形成包括基板的一部分的沟槽。 成核层沉积在沟槽内的衬底部分上。 在成核层上沉积III-N材料层。 在沟槽上横向生长III-N材料层。 器件层沉积在横向生长的III-N材料层上。 在横向生长的材料上获得低缺陷密度区域，并用于Si衬底上的III-N材料的电子器件制造。
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