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    Polarization-induced barriers for N-face nitride-based electronics
    52.
    发明授权
    Polarization-induced barriers for N-face nitride-based electronics 失效
    用于N面氮化物基电子器件的极化诱导屏障

    公开(公告)号：US08039352B2

    公开(公告)日：2011-10-18

    申请号：US12127661

    申请日：2008-05-27

    Applicant: Umesh K. Mishra ,  Tomas A. Palacios Gutierrez ,  Man-Hoi Wong

    Inventor： Umesh K. Mishra ,  Tomas A. Palacios Gutierrez ,  Man-Hoi Wong

    IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/338

    CPC classification number: H01L29/7783 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

    Abstract: A method for fabricating a potential barrier for a nitrogen-face (N-face) nitride-based electronic device, comprising using a thickness and polarization induced electric field of a III-nitride interlayer, positioned between a first III-nitride layer and a second III-nitride layer, to shift, e.g., raise or lower, the first III-nitride layer's energy band with respect to the second III-nitride layer's energy band by a pre-determined amount. The first III-nitride layer and second III-nitride layer each have a higher or lower polarization coefficient than the III-nitride interlayer's polarization coefficient.

    Abstract translation: 一种用于制造氮 - 面（N面）氮化物基电子器件的势垒的方法，包括使用位于第一III族氮化物层和第二层氮化物层之间的III族氮化物中间层的厚度和极化感应电场 III族氮化物层相对于第二III族氮化物层的能带移动（例如）升高或降低第一III族氮化物层的能带预定量。 第一III族氮化物层和第二III族氮化物层各自具有比III族氮化物夹层的极化系数更高或更低的偏振系数。

    Fabrication of single or multiple gate field plates
    55.
    发明授权
    Fabrication of single or multiple gate field plates 有权
    制造单栅极或多栅极场板

    公开(公告)号：US07812369B2

    公开(公告)日：2010-10-12

    申请号：US10570964

    申请日：2004-09-09

    Applicant: Alessandro Chini ,  Umesh K. Mishra ,  Primit Parikh ,  Yifeng Wu

    Inventor： Alessandro Chini ,  Umesh K. Mishra ,  Primit Parikh ,  Yifeng Wu

    IPC: H01L29/778

    CPC classification number: H01L29/404 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/401 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42312 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/785

    Abstract: A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.

    Abstract translation: 使用在场效应晶体管的表面上的介电材料沉积/生长，介电材料蚀刻和金属蒸发的连续步骤来制造单栅极或多栅极场板的工艺。 这种制造工艺允许对场板操作的严格控制，因为介电材料沉积/生长通常是良好可控的工艺。 此外，沉积在器件表面上的电介质材料不需要从器件本征区域去除：这基本上使得能够实现电镀设备，而不需要低损耗介电材料干/湿蚀刻。 使用多个栅极场板还通过多个连接降低栅极电阻，从而提高大的周边和/或亚微米栅极器件的性能。

    Fabrication of self-aligned, T-gate HEMT
    59.
    发明授权
    Fabrication of self-aligned, T-gate HEMT 失效
    自对准，T型门HEMT的制造

    公开(公告)号：US5053348A

    公开(公告)日：1991-10-01

    申请号：US444708

    申请日：1989-12-01

    Applicant: Umesh K. Mishra ,  Mark A. Thompson ,  Linda M. Jelloian

    Inventor： Umesh K. Mishra ,  Mark A. Thompson ,  Linda M. Jelloian

    IPC: H01L29/812 ,  H01L21/28 ,  H01L21/285 ,  H01L21/335 ,  H01L21/338

    CPC classification number: H01L29/66462 ,  H01L21/28587 ,  Y10S148/10 ,  Y10S148/102 ,  Y10S148/143 ,  Y10S438/951

    Abstract: A generally T-shaped gate is formed by electron beam irradiation of a multilevel resist structure on a substrate. The resist structure has an upper layer which is more sensitive to the electron beam than a lower layer thereof. A generally T-shaped opening is formed in the resist structure by etching of the irradiated areas. An electrically conductive metal is deposited to fill the opening and thereby form a T-shaped gate on the substrate. After the resist layer structure and metal deposited thereon is removed, a masking layer is formed on the substrate around the gate, having an opening therethrough which is aligned with and wider than the cross section of the gate, and defining first and second lateral spacings between opposite extremities of the cross section and adjacent edges of the opening. Deposition of an electrically conductive metal forms source and drain metallizations on the substrate on areas underlying the first and lateral spacings respectively. The metallizations are self-aligned to the gate and separated therefrom by the masking effect of the gate during the metal deposition. The gate may have an asymmetrical top section which provides a larger spacing between the gate and drain metallization than between the gate and source metallization to increase the breakdown voltage of the device. Insulative oxide sidewalls may be formed on the gate.

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