公开(公告)号：US11769696B2

公开(公告)日：2023-09-26

申请号：US17873605

申请日：2022-07-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chun-Yuan Chen ,  Li-Zhen Yu ,  Huan-Chieh Su ,  Lo-Heng Chang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC分类号： H01L21/8234 ,  H01L21/768 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/823418 ,  H01L21/7682 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696 ,  H01L29/6681

摘要： During a front side process of a wafer, a hard mask layer is formed under a metal portion of a semiconductor device, and an epitaxial layer is deposited to form epitaxial portions of the semiconductor device. In a back side process of the wafer to cut the epitaxial layer, the metal portion is covered and protected by the hard mask layer from damages during etching of the epitaxial layer.

公开(公告)号：US20230299180A1

公开(公告)日：2023-09-21

申请号：US18311071

申请日：2023-05-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO, LTD.

发明人： Wei-Min LIU ,  Yee-Chia YEO ,  Li-Li SU

IPC分类号： H01L29/66 ,  H01L29/04 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/6681 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/7851

摘要： The present disclosure is directed to methods for forming source/drain (S/D) epitaxial structures with a hexagonal shape. The method includes forming a fin structure that includes a first portion and a second portion proximate to the first portion, forming a gate structure on the first portion of the fin structure, and recessing the second portion of the fin structure. The method further includes growing a S/D epitaxial structure on the recessed second portion of the fin structure, where growing the S/D epitaxial structure includes exposing the recessed second portion of the fin structure to a precursor and one or more reactant gases to form a portion of the S/D epitaxial structure. Growing the S/D epitaxial structure further includes exposing the portion of the S/D structure to an etching chemistry and exposing the portion of the S/D epitaxial structure to a hydrogen treatment to enhance growth of the S/D epitaxial structure.

公开(公告)号：US11756999B2

公开(公告)日：2023-09-12

申请号：US17205670

申请日：2021-03-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC分类号： H01L29/06 ,  H01L27/092 ,  H01L27/02 ,  H01L21/033 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  G06F30/392

CPC分类号： H01L29/0696 ,  G06F30/392 ,  H01L21/0337 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/7851

摘要： In at least one cell region, a semiconductor device includes fin patterns and at least one overlying gate structure. The fin patterns (dummy and active) are substantially parallel to a first direction. Each gate structure is substantially parallel to a second direction (which is substantially perpendicular to the first direction). First and second active fin patterns have corresponding first and second conductivity types. Each cell region, relative to the second direction, includes: a first active region which includes a sequence of three or more consecutive first active fin patterns located in a central portion of the cell region; a second active region which includes one or more second active fin patterns located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fin patterns located between the first active region and a second edge of the cell region.

公开(公告)号：US11749745B2

公开(公告)日：2023-09-05

申请号：US17219982

申请日：2021-04-01

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Xiang Hu

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L29/6681 ,  H01L21/823431 ,  H01L29/7851

摘要： A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate, and a first dielectric layer, a first gate structure and a plurality of second gate structures over the substrate. A second protection layer is formed on a top of a second gate structure. A first source-drain doped layer is formed between the first gate structure and an adjacent second gate structure. The first dielectric layer covers sidewalls of the first and second gate structures, and exposes a top surface of the second protection layer. The semiconductor structure also includes a first conductive structure in the first dielectric layer over the first source-drain doped layer, and a conductive layer on the first gate structure and the first conductive structure. A top surface of the conductive layer is coplanar with a top surface of the first dielectric layer.

公开(公告)号：US11749742B2

公开(公告)日：2023-09-05

申请号：US17182651

申请日：2021-02-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsungyu Hung ,  Pang-Yen Tsai ,  Pei-Wei Lee

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/306 ,  H01L29/423

CPC分类号： H01L29/66553 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/7853 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/42392

摘要： Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the fin includes a channel region and a source/drain region; forming a dummy gate structure over the substrate and the fin; etching a portion of the fin in the source/drain region; selectively removing an edge portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed, and an edge portion of the first semiconductor layer is suspended; performing a reflow process to the first semiconductor layer to form an inner spacer, wherein the inner spacer forms sidewall surfaces of the source/drain region of the fin; and epitaxially growing a sour/drain feature in the source/drain region.

公开(公告)号：US11742416B2

公开(公告)日：2023-08-29

申请号：US17332025

申请日：2021-05-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Hao Lin ,  Chia-Hung Chou ,  Chih-Hsuan Chen ,  Ping-En Cheng ,  Hsin-Wen Su ,  Chien-Chih Lin ,  Szu-Chi Yang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/6681 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/6656 ,  H01L29/66553 ,  H01L29/7851

摘要： A semiconductor structure includes: a semiconductor substrate; a first source/drain feature and a second source/drain feature over the semiconductor substrate; and semiconductor layers extending longitudinally in a first direction and connecting the first source/drain feature and the second source/drain feature. The semiconductor layers are spaced apart from each other in a second direction perpendicular to the first direction. The semiconductor structure further includes inner spacers each between two adjacent semiconductor layers; metal oxide layers interposing between the inner spacers and the semiconductor layers; and a gate structure wrapping around the semiconductor layers and the metal oxide layers.

公开(公告)号：US11742415B2

公开(公告)日：2023-08-29

申请号：US17178006

申请日：2021-02-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Cheng Ching ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L27/088 ,  H01L29/78 ,  H01L21/308

CPC分类号： H01L29/6681 ,  H01L21/3086 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/785

摘要： FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.

公开(公告)号：US11742244B2

公开(公告)日：2023-08-29

申请号：US17093350

申请日：2020-11-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Sheng Fan ,  Chun-Yen Lin ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L21/823437 ,  H01L21/823431 ,  H01L29/6681 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell boundary is increased by changing a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary. Alternatively, in some cases, the threshold voltage at the cell boundary is increased by performing a threshold voltage implant (e.g., an ion implant) at the cell boundary, and into a dummy gate disposed at the cell boundary. Further, in some embodiments, the threshold voltage at the cell boundary is increased by use of a silicon germanium (SiGe) channel at the cell boundary. In some cases, the SiGe may be disposed within the substrate at the cell boundary and/or the SiGe may be part of the dummy gate disposed at the cell boundary.

公开(公告)号：US20230268426A1

公开(公告)日：2023-08-24

申请号：US17676470

申请日：2022-02-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wan-Yi Kao ,  Hung Cheng Lin ,  Che-Hao Chang ,  Yung-Cheng Lu ,  Chi On Chui

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC分类号： H01L29/6681 ,  H01L29/7851 ,  H01L21/02164 ,  H01L21/02167

摘要： A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, where the first semiconductor fin and the second semiconductor fin extend upwards from a semiconductor substrate, depositing a second dielectric layer over the first dielectric layer, depositing a third dielectric layer over the second dielectric layer, where materials of the second dielectric layer and the third dielectric layer are different, and a material of the first dielectric layer is different from the material of the second dielectric layer and recessing the first dielectric layer and the second dielectric layer to expose sidewalls of the first semiconductor fin and the second semiconductor fin and to form a dummy fin between the first semiconductor fin and the second semiconductor fin.

公开(公告)号：US11735669B2

公开(公告)日：2023-08-22

申请号：US17094904

申请日：2020-11-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Yi Chuang ,  Hou-Yu Chen ,  Kuan-Lun Cheng

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L21/0245 ,  H01L21/02293 ,  H01L21/02532 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823487 ,  H01L29/6681 ,  H01L29/66818

摘要： A semiconductor device according to the present disclosure includes a first transistor and a second transistor disposed over the first transistor. The first transistor includes a plurality of channel members vertically stacked over one another, and a first source/drain feature adjoining the plurality of channel members. The second transistor includes a fin structure, and a second source/drain feature adjoining the fin structure. The semiconductor device further includes a conductive feature electrically connecting the first source/drain feature and the second source/drain feature.