公开(公告)号：US09666696B2

公开(公告)日：2017-05-30

申请号：US14935139

申请日：2015-11-06

申请人： Infineon Technologies Austria AG

发明人： Romain Esteve ,  Cédric Ouvrard

IPC分类号： H01L29/66 ,  H01L29/808 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L21/02 ,  H01L21/04 ,  H01L29/16 ,  H01L29/20

CPC分类号： H01L29/66909 ,  H01L21/02378 ,  H01L21/0465 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/8083

摘要： A method of manufacturing a vertical junction field effect transistor (JFET) includes forming a drain in a semiconductor substrate, forming a compound semiconductor epitaxial layer on the semiconductor substrate, and forming a source, a gate, a drift region, and a body diode all in the same compound semiconductor epitaxial layer. The drain is vertically spaced apart from the source and the gate by the drift region. The body diode is connected between the drain and the source.

公开(公告)号：US20170110556A1

公开(公告)日：2017-04-20

申请号：US15372758

申请日：2016-12-08

申请人： Renesas Electronics Corporation

发明人： Kouichi Arai

IPC分类号： H01L29/66 ,  H01L29/16 ,  H01L29/10 ,  H01L29/808 ,  H01L21/04

CPC分类号： H01L29/66068 ,  H01L21/046 ,  H01L21/8213 ,  H01L21/8232 ,  H01L27/098 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66909 ,  H01L29/8083

摘要： A method of manufacturing a semiconductor device that includes a junction field effect transistor, the junction field effect transistor including a semiconductor substrate of a first conductivity type, an epitaxial layer of the first conductivity type formed on the semiconductor substrate, a source region of the first conductivity type formed on a surface of the epitaxial layer, a channel region of the first conductivity type formed in a lower layer of the source region, a pair of trenches formed in the epitaxial layer so as to sandwich the source region therebetween, and a pair of gate regions of a second conductivity type, opposite to the first conductivity type, formed below a bottom of the pair of trenches.

公开(公告)号：US20170018627A1

公开(公告)日：2017-01-19

申请号：US15266210

申请日：2016-09-15

申请人： United Silicon Carbide, Inc.

发明人： Zhongda Li ,  Anup Bhalla

IPC分类号： H01L29/66 ,  H01L29/808 ,  H01L21/04 ,  H01L21/768

CPC分类号： H01L29/8083 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/045 ,  H01L21/046 ,  H01L21/0465 ,  H01L21/047 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/76897 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66909

摘要： A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A maskless self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

摘要翻译： 使用有限数量的掩模的工艺制成的垂直JFET。 第一掩模用于同时在活性细胞和终止区域中形成台面和沟槽。 无掩模自对准工艺用于形成硅化物源极和栅极接触。 第二个掩码用于打开窗口到联系人。 第三个掩模用于图案覆盖金属化。 使用可选的第四个掩模来图案化钝化。 可选地，可以通过成角度的注入来掺杂沟道，并且活性单元区域中的沟槽和台面的宽度可以与端接区域中的那些不同。

公开(公告)号：US09385195B1

公开(公告)日：2016-07-05

申请号：US14675536

申请日：2015-03-31

申请人： STMICROELECTRONICS, INC.

发明人： John H. Zhang

IPC分类号： H01L29/745 ,  H01L27/148 ,  H01L21/00 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/10 ,  H01L29/49 ,  H01L29/20 ,  H01L29/66 ,  H01L21/28

CPC分类号： H01L27/10879 ,  B82Y10/00 ,  H01L21/28008 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823885 ,  H01L21/823892 ,  H01L27/0814 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/66909 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/1233 ,  H01L2029/7858

摘要： A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

摘要翻译： 垂直隧道FET（TFET）为关键尺寸低于7nm的晶体管提供低功耗，高速开关性能。 垂直TFET使用全栅（GAA）器件结构，其具有在形成于硅衬底中的掺杂阱的表面上方延伸的圆柱形结构。 圆柱形结构包括从掺杂阱外延生长的下部漏极区域，沟道和上部源极区域。 该通道由本征硅制成，而源极和漏极区域原位掺杂。 环形栅极围绕通道，电容性地控制从所有侧面通过通道的电流。 源极可以通过前侧触点电接触，而漏极通过背面触点进行访问，该触点提供低接触电阻并且还用作散热器。 垂直TFET集成电路的可靠性通过将垂直TFET耦合到静电放电（ESD）二极管来增强。

公开(公告)号：US09384983B2

公开(公告)日：2016-07-05

申请号：US14729407

申请日：2015-06-03

申请人： Infineon Technologies AG

发明人： Ralf Siemieniec ,  Jens Peter Konrath

IPC分类号： H01L29/872 ,  H01L21/266 ,  H01L29/861 ,  H01L29/06 ,  H01L29/808 ,  H01L21/768 ,  H01L29/66 ,  H01L21/04 ,  H01L29/16

CPC分类号： H01L21/266 ,  H01L21/0465 ,  H01L21/76895 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66121 ,  H01L29/66128 ,  H01L29/66143 ,  H01L29/66893 ,  H01L29/66909 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/8618 ,  H01L29/872

摘要： A method for producing a vertical semiconductor device includes providing a semiconductor substrate having a first surface and comprising an n-doped first semiconductor layer, forming a hard mask on the first surface, the hard mask comprising openings defining first zones in the n-doped first semiconductor layer, implanting acceptor ions of a first maximum energy through the hard mask into the first zones, replacing the hard mask by an inverted mask comprising openings that are substantially complementary to the openings of the hard mask; implanting acceptor ions of a second maximum energy different to the first maximum energy through the inverted mask into second zones of the n-doped first semiconductor layer, and carrying out at least one temperature step to activate the acceptor ions in the first zones and the second zones.

摘要翻译： 一种用于制造垂直半导体器件的方法包括提供具有第一表面并包括n掺杂的第一半导体层的半导体衬底，在第一表面上形成硬掩模，所述硬掩模包括在n掺杂的第一表面中限定第一区的开口 通过硬掩模将第一最大能量的受主离子注入到第一区域中，通过包括与硬掩模的开口基本上互补的开口的倒置掩模代替硬掩模; 将与第一最大能量不同的第二最大能量的受体离子通过反相掩模注入到n掺杂的第一半导体层的第二区域中，并且执行至少一个温度步骤以激活第一区域中的受主离子， 区域。

公开(公告)号：US20160155738A1

公开(公告)日：2016-06-02

申请号：US15015564

申请日：2016-02-04

申请人： JOHN V. VELIADIS

发明人： JOHN V. VELIADIS

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L29/808 ,  H01L29/06 ,  H01L21/8234

CPC分类号： H01L27/088 ,  G06F8/33 ,  G06F8/72 ,  G06F8/75 ,  H01L21/8232 ,  H01L21/823418 ,  H01L21/823487 ,  H01L27/098 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66045 ,  H01L29/66068 ,  H01L29/66909 ,  H01L29/66924 ,  H01L29/8083

摘要： A monolithic bi-directional device provides bi-directional power flow and bi-directional blocking of high-voltages. The device includes a first transistor having a first drain formed over a first channel layer that overlays a substrate, and a second transistor that includes a second drain formed over a second channel layer that overlays the substrate. The substrate forms a common source for both the first transistor and the second transistor.

摘要翻译： 单片双向器件提供双向功率流和双向阻断高电压。 该器件包括第一晶体管，其具有形成在覆盖衬底的第一沟道层上的第一漏极，以及第二晶体管，其包括形成在覆盖衬底的第二沟道层上的第二漏极。 衬底形成用于第一晶体管和第二晶体管的公共源极。

公开(公告)号：US20160064534A1

公开(公告)日：2016-03-03

申请号：US14935139

申请日：2015-11-06

申请人： Infineon Technologes Austria AG

发明人： Romain Esteve ,  Cédric Ouvrard

IPC分类号： H01L29/66 ,  H01L21/04 ,  H01L21/02

CPC分类号： H01L29/66909 ,  H01L21/02378 ,  H01L21/0465 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/8083

摘要： A method of manufacturing a vertical junction field effect transistor (JFET) includes forming a drain in a semiconductor substrate, forming a compound semiconductor epitaxial layer on the semiconductor substrate, and forming a source, a gate, a drift region, and a body diode all in the same compound semiconductor epitaxial layer. The drain is vertically spaced apart from the source and the gate by the drift region. The body diode is connected between the drain and the source.

摘要翻译： 制造垂直结型场效应晶体管（JFET）的方法包括：在半导体衬底中形成漏极，在半导体衬底上形成化合物半导体外延层，以及形成源极，栅极，漂移区域和体二极管 在相同的化合物半导体外延层中。 漏极与源极和栅极垂直间隔开漂移区。 体二极管连接在漏极和源极之间。

公开(公告)号：US09230956B2

公开(公告)日：2016-01-05

申请号：US14066626

申请日：2013-10-29

申请人： Chengdu Monolithic Power Systems Co., Ltd.

发明人： Rongyao Ma ,  Tiesheng Li ,  Lei Zhang ,  Daping Fu

IPC分类号： H01L27/06 ,  H01L27/146 ,  H01L27/098

CPC分类号： H01L27/0617 ,  H01L27/098 ,  H01L27/14679 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/24 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/66909 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/7832 ,  H01L29/8083

摘要： A JFET having a semiconductor substrate of a first doping type, an epitaxial layer of the first doping type located on the semiconductor substrate, a body region of a second doping type located in the epitaxial layer, a source region of the first doping type located in the epitaxial layer, a gate region of the second doping type located in the body region, and a shielding layer of the second doping type located in the epitaxial layer, wherein the semiconductor substrate is configured as a drain region, the shielding layer is in a conductive path formed between the source region and the drain region.

摘要翻译： 具有第一掺杂型半导体衬底的JFET，位于半导体衬底上的第一掺杂型的外延层，位于外延层中的第二掺杂型的体区，位于第一掺杂类型的源区 外延层，位于体区的第二掺杂型的栅极区域和位于外延层中的第二掺杂型的屏蔽层，其中半导体衬底被配置为漏极区，屏蔽层为 形成在源极区域和漏极区域之间的导电路径。

公开(公告)号：US09171751B2

公开(公告)日：2015-10-27

申请号：US14264998

申请日：2014-04-29

申请人： AVOGY, INC.

发明人： Donald R. Disney ,  Andrew P. Edwards ,  Hui Nie ,  Richard J. Brown ,  Isik C. Kizilyalli ,  David P. Bour ,  Linda Romano ,  Thomas R. Prunty

IPC分类号： H01L29/06 ,  H01L21/761 ,  H01L21/266 ,  H01L21/265 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/808 ,  H01L29/872

CPC分类号： H01L21/761 ,  H01L21/2654 ,  H01L21/266 ,  H01L21/765 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66136 ,  H01L29/66212 ,  H01L29/6631 ,  H01L29/66909 ,  H01L29/8083 ,  H01L29/872

摘要： A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.

摘要翻译： 一种用于制造边缘终端结构的方法包括提供具有第一表面和第二表面和第一导电类型的衬底，形成耦合到衬底的第一表面的第一导电类型的第一GaN外延层，并形成第二 与第一导电类型相反的第二导电类型的GaN外延层。 第二GaN外延层耦合到第一GaN外延层。 该方法还包括将离子注入第二GaN外延层的第一区域以将第二GaN外延层的第二区域与第二GaN外延层的第三区域电隔离。 该方法还包括形成耦合到第二GaN外延层的第二区域并形成耦合到第二GaN外延层的第三区域的边缘端接结构的有源器件。

公开(公告)号：US20150263178A1

公开(公告)日：2015-09-17

申请号：US14207733

申请日：2014-03-13

申请人： Infineon Technologies AG

发明人： Jens Peter Konrath ,  Hans-Joachim Schulze ,  Ralf Siemieniec ,  Cedric Ouvrard

IPC分类号： H01L29/808 ,  H01L21/311 ,  H01L21/266 ,  H01L29/66

CPC分类号： H01L29/8083 ,  H01L21/266 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/407 ,  H01L29/66909

摘要： A JFET has a semiconductor body with a first surface and second surface substantially parallel to the first surface. A source metallization and gate metallization are arranged on the first surface. A drain metallization is arranged on the second surface. In a sectional plane substantially perpendicular to the first surface, the semiconductor body includes: a first semiconductor region in ohmic contact with the source and drain metallizations, at least two second semiconductor regions in ohmic contact with the gate metallization, spaced apart from one another, and forming respective first pn-junctions with the first semiconductor region, and at least one body region forming a second pn-junction with the first semiconductor region. The at least one body region is in ohmic contact with the source metallization. At least a portion of the at least one body region is, in a projection onto the first surface, arranged between the two second semiconductor regions.

摘要翻译： JFET具有半导体本体，其具有基本上平行于第一表面的第一表面和第二表面。 源金属化和栅极金属化被布置在第一表面上。 漏极金属化被布置在第二表面上。 在基本上垂直于第一表面的截面中，半导体本体包括：与源极和漏极金属化欧姆接触的第一半导体区域，与栅极金属化欧姆接触的至少两个第二半导体区域彼此间隔开， 以及与所述第一半导体区域形成相应的第一pn结，以及形成与所述第一半导体区域的第二pn结的至少一个体区。 至少一个体区与源金属化欧姆接触。 所述至少一个体区的至少一部分在所述第一表面上的突起中布置在所述两个第二半导体区之间。