公开(公告)号：US09515669B2

公开(公告)日：2016-12-06

申请号：US15047778

申请日：2016-02-19

Applicant: Microsemi SoC Corporation

Inventor： Prakash Reddy

IPC: H03L7/06 ,  H03L7/10 ,  H03L7/099 ,  H03L7/087

CPC classification number: H03L7/103 ,  H03L7/087 ,  H03L7/093 ,  H03L7/0991

Abstract: A digital phased lock loop includes a digital controlled oscillator configured to produce an output signal at a frequency. A phase comparator compares the output signal, or a signal derived therefrom, with a reference signal to produce a phase error signal. A first loop filter produces a first control signal for the digital controlled oscillator from an output of the phase comparator. A frequency error measuring circuit coupled to the output of the phase comparator produces a frequency error signal. A second loop filter produces a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit. A circuit combines the first and second control signals and provides the combined control signals to the digital controlled oscillator.

Abstract translation: 数字相位锁定环包括配置成以频率产生输出信号的数字控制振荡器。 相位比较器将输出信号或由其导出的信号与参考信号进行比较，以产生相位误差信号。 第一环路滤波器从相位比较器的输出产生数字控制振荡器的第一控制信号。 耦合到相位比较器的输出的频率误差测量电路产生频率误差信号。 第二环路滤波器从频率误差测量电路的输出产生数字控制振荡器的第二控制信号。 电路组合第一和第二控制信号，并将组合的控制信号提供给数字控制振荡器。

公开(公告)号：US20160336943A1

公开(公告)日：2016-11-17

申请号：US14713174

申请日：2015-05-15

Applicant: INTEL CORPORATION

Inventor： FANGXING WEI ,  MICHAEL J. ALLEN ,  SETUL M. SHAH

IPC: H03L7/099

CPC classification number: H03L7/0991 ,  H03L7/087 ,  H03L7/093 ,  H03L7/095 ,  H03L7/0995 ,  H03L2207/50

Abstract: A glitch-free digitally controlled oscillator (DCO) code update may be achieved by synchronizing the transfer of the DCO code update to a logic state transition of a pulse in the DCO clock output signal such that the code update may be achieved while the DCO delay chain remains in the same logic state. A state machine may provide the DCO code update and a pulsed update signal to a timing circuit. The DCO code update may be aligned with a pulse in the pulsed update signal. The timing circuit may generate a DCO code update enabled signal upon alignment of the pulse in the pulsed update signal with a state transition of a pulse in the pulsed DCO clock output. The DCO code update enabled signal may be aligned with a state transition in the pulsed DCO clock output to permit a glitch-free DCO code update.

Abstract translation: 可以通过将DCO代码更新的传送同步到DCO时钟输出信号中的脉冲的逻辑状态转换来实现无毛刺的数字控制振荡器（DCO）代码更新，使得可以在DCO延迟期间实现代码更新 链条保持在相同的逻辑状态。 状态机可以将DCO代码更新和脉冲更新信号提供给定时电路。 DCO代码更新可以与脉冲更新信号中的脉冲对准。 定时电路可以在脉冲更新信号中的脉冲与脉冲DCO时钟输出中的脉冲的状态转换对齐时产生DCO代码更新使能信号。 DCO代码更新使能信号可以与脉冲DCO时钟输出中的状态转换对齐，以允许无毛刺的DCO代码更新。

公开(公告)号：US09461656B2

公开(公告)日：2016-10-04

申请号：US14558072

申请日：2014-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Yoon Joo ,  Seung-Jun Bae ,  Young-Soo Sohn ,  Ho-Sung Song ,  Jeong-Don Ihm

IPC: H03L7/06 ,  H03L7/087 ,  H03L7/07 ,  H03L7/083 ,  H03L7/099 ,  G11C7/22

CPC classification number: H03L7/087 ,  G11C7/222 ,  H03L7/07 ,  H03L7/083 ,  H03L7/0995

Abstract: An injection-locked phase-locked loop (ILPLL) circuit includes a delay-locked loop (DLL) and an ILPLL. The DLL is configured to generate a DLL clock by performing a delay-locked operation on a reference clock. The ILPLL includes a voltage-controlled oscillator (VCO), and is configured to generate an output clock by performing an injection synchronous phase-locked operation on the reference clock. The DLL clock is injected into the VCO as an injection clock of the VCO.

Abstract translation: 注射锁相环（ILPLL）电路包括延迟锁定环（DLL）和ILPLL。 DLL被配置为通过对参考时钟执行延迟锁定操作来生成DLL时钟。 ILPLL包括压控振荡器（VCO），并且被配置为通过对参考时钟执行注入同步锁相操作来产生输出时钟。 将DLL时钟作为VCO的注入时钟注入到VCO中。

公开(公告)号：US09432028B2

公开(公告)日：2016-08-30

申请号：US14716106

申请日：2015-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Jin Kim ,  Chang Hoon Baek ,  Sang Kyu Lee ,  Jae Youl Lee

IPC: H03D3/24 ,  H03L7/08 ,  H03L7/089 ,  H03L7/093 ,  H03L7/091 ,  H03L7/099 ,  H03L7/187

CPC classification number: H03L7/0807 ,  H03L1/00 ,  H03L7/087 ,  H03L7/089 ,  H03L7/091 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/0995 ,  H03L7/113 ,  H03L7/187 ,  H03L2207/06 ,  H03L2207/50

Abstract: A clock data recovery circuit including: a digital phase detector and deserializer configured to sample serial data using a recovery clock signal to generate an up phase error signal and a down phase error signal which correspond to a phase difference between the serial data and the recovery clock signal; a digital loop filter configured to generate an up fine code and a down fine code based on a result of counting the up and down phase error signals; a loop combiner configured to generate an up fine tuning code and a down fine tuning code by using the up and down phase error signals and the up and down fine codes; and a digitally controlled oscillator configured to generate the recovery clock signal having a frequency changed with the up and down fine tuning codes.

Abstract translation: 一种时钟数据恢复电路，包括：数字相位检测器和解串器，被配置为使用恢复时钟信号对串行数据进行采样，以产生对应于串行数据和恢复时钟之间的相位差的上相位误差信号和下行相位误差信号 信号; 数字环路滤波器，其被配置为基于对所述上下相位误差信号进行计数的结果来生成上位编码和下精细码; 配置为通过使用上下相位误差信号和上下精细码产生上调微调码和下调微调码的环路组合器; 以及数字控制振荡器，被配置为产生具有随着上下微调代码而改变的频率的恢复时钟信号。

公开(公告)号：US09397674B2

公开(公告)日：2016-07-19

申请号：US14145493

申请日：2013-12-31

Applicant: LSI Corporation

Inventor： Pervez M. Aziz ,  Shiva Prasad Kotagiri ,  Sundeep Venkatraman ,  Sunil Srinivasa ,  Amaresh V. Malipatil

IPC: H03D3/24 ,  H03L7/087 ,  H03L7/06

CPC classification number: H03L7/087 ,  H03L7/06 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/093 ,  H04L7/0058 ,  H04L7/033

Abstract: A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples.

Abstract translation: 时钟和数据恢复装置包括相位检测器，量化器和环路滤波器。 相位检测器在表示相位调整时钟和输入数据信号之间的相位差的输出端产生相位误差采样。 量化器耦合到相位检测器的输出并响应于高阈值和低阈值，在输出端产生三值量化的相位误差样本。 环路滤波器对量化的相位误差样本或相位误差采样进行滤波，以控制相位控制时钟。 确定输入数据信号中存在的抖动频率的频率检测器寻址查找表以提供抖动频率相关的高和低阈值，并且控制环路滤波器处理哪些相位误差采样。 频率检测器通过取低通滤波相位误差样本的峰值比来确定抖动频率。

公开(公告)号：US09374217B1

公开(公告)日：2016-06-21

申请号：US14853912

申请日：2015-09-14

Applicant: INPHI CORPORATION

Inventor： Simon Forey ,  Parmanand Mishra

IPC: H03D3/24 ,  H04L7/033 ,  H04L7/00

CPC classification number: H04L7/0331 ,  H03L7/087 ,  H03M9/00 ,  H04L7/033

Abstract: The present application is directed to data communication. More specifically, embodiments of the present invention provide a SerDes system that includes multiple communication lanes that are aligned using a clock signal. Each of the communication lanes comprises a receiver, a buffer, and a transmitter. The receiver uses multiple sampling lanes for data sampling and clock recovery. Sampled data are stored at the buffer and transmitted by the transmitter. There are other embodiments as well.

Abstract translation: 本申请涉及数据通信。 更具体地，本发明的实施例提供了一种SerDes系统，其包括使用时钟信号对准的多个通信通道。 每个通信通道包括接收器，缓冲器和发射器。 接收机使用多个采样通道进行数据采样和时钟恢复。 采样数据存储在缓冲区并由发送器发送。 还有其它实施例。

公开(公告)号：US20160164527A1

公开(公告)日：2016-06-09

申请号：US14955802

申请日：2015-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-young SONG ,  Tae-ik KIM ,  Ji-hyun KIM

IPC: H03L7/081 ,  H03L7/095 ,  H03L7/08 ,  H03L7/099

CPC classification number: H03L7/0814 ,  H03L7/0802 ,  H03L7/081 ,  H03L7/087 ,  H03L7/095 ,  H03L7/099 ,  H03L7/0992 ,  H03L7/193 ,  H03L2207/06

Abstract: Provided are a digital phase-locked loop (DPLL) having improved signal characteristics, and a method of operating the DPLL. The DPLL includes a first tracking unit configured to receive a reference signal and a feedback signal that is generated by feeding back an output signal of the DPLL, track the feedback signal, and output a delayed reference signal, and a second tracking unit configured to receive a delayed feedback signal generated by delaying the feedback signal, and the delayed reference signal, and generate an output signal of the DPLL, of which a frequency is controlled according to a phase difference between the delayed feedback signal and the delayed reference signal.

Abstract translation: 提供了具有改进的信号特性的数字锁相环（DPLL）以及操作DPLL的方法。 DPLL包括：第一跟踪单元，被配置为接收参考信号和通过反馈DPLL的输出信号，跟踪反馈信号并输出​​延迟的参考信号而产生的反馈信号;以及第二跟踪单元，被配置为接收 通过延迟反馈信号产生的延迟反馈信号和延迟的参考信号，并产生DPLL的输出信号，其根据延迟的反馈信号和延迟的参考信号之间的相位差来控制频率。

公开(公告)号：US09344097B2

公开(公告)日：2016-05-17

申请号：US14726753

申请日：2015-06-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mustafa Ulvi Erdogan ,  Sridhar Ramaswamy

IPC: H04L7/033 ,  H03L7/08 ,  H03L7/087

CPC classification number: H03L7/0807 ,  H03L7/087 ,  H03L7/089 ,  H04L7/0004 ,  H04L7/033 ,  H04L7/0331

Abstract: A phase-frequency detector (PFD) circuit that includes a binary phase detector and a ternary phase detector coupled to the binary phase detector. The binary phase detector is configured to, based on the PFD circuit being in a frequency acquisition state, compare a clock signal with a data signal and output up and down signals based on the comparison. The binary phase detector is also configured to be disabled based on the PFD circuit being in a frequency locked state. The ternary phase detector is configured to compare the clock signal with the data signal and output up, down, and hold signals based on the comparison.

Abstract translation: 相位频率检测器（PFD）电路，包括二进制相位检测器和耦合到二进制相位检测器的三相检测器。 二值相位检测器被配置为基于PFD电路处于频率获取状态，将时钟信号与数据信号进行比较，并根据比较输出上下信号。 二进制相位检测器也被配置为基于PFD电路处于锁频状态而被禁用。 三元相位检测器被配置为将时钟信号与数据信号进行比较，并根据比较输出上，下和保持信号。

公开(公告)号：US09325490B2

公开(公告)日：2016-04-26

申请号：US14221162

申请日：2014-03-20

Applicant: STMicroelectronics International N.V.

Inventor： Anurag Tiwari ,  Kallol Chatterjee

IPC: H03D3/24 ,  H04L7/027 ,  H03L7/087 ,  H04L7/033

CPC classification number: H04L7/027 ,  H03L7/087 ,  H03L7/22 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/0332

Abstract: A circuit and method for referenceless CDR with improved efficiency and jitter tolerance by using an additional loop for frequency detection. Such an improved circuit includes a frequency detector for identifying whether an initial recovered clock signal is faster or slower than the actual bit rate of the received data stream. The frequency detector provides a jitter tolerance of +/−0.5 UI and uses significantly fewer components that other conventional frequency detectors. Having fewer components, significantly less power is also consumed. In an embodiment, the FD uses only four flip-flops, two AND gates, and one delay circuit. Having fewer components also uses less die space in integrated circuits. Having high jitter tolerance and fewer components is an improvement over conventional referenceless CDR circuits.

Abstract translation: 一种用于无参考CDR的电路和方法，通过使用用于频率检测的附加回路来提高效率和抖动容限。 这种改进的电路包括用于识别初始恢复的时钟信号是否比接收的数据流的实际比特率更快或更慢的频率检测器。 频率检测器提供+/- 0.5 UI的抖动容限，并且使用其他常规频率检测器的显着较少的组件。 组件数量较少，功耗明显降低。 在一个实施例中，FD仅使用四个触发器，两个与门和一个延迟电路。 在集成电路中使用更少的组件也减少了管芯空间。 具有高抖动容限和更少的组件是比传统的无参考CDR电路的改进。

公开(公告)号：US20160105188A1

公开(公告)日：2016-04-14

申请号：US14837731

申请日：2015-08-27

Applicant: JONG-PIL CHO ,  YOUNG-JOO LEE

Inventor： JONG-PIL CHO ,  YOUNG-JOO LEE

IPC: H03L7/087 ,  H04L7/00 ,  H04B5/00 ,  H04L7/033 ,  H03L7/089 ,  H03L7/099

CPC classification number: H03L7/087 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/18 ,  H03L7/23 ,  H04B5/0025 ,  H04B5/0031 ,  H04B5/0056 ,  H04L7/0008

Abstract: A semiconductor device including a PLL providing candidate clocks of different phases in response to a first clock received from a reader via an antenna, a phase difference detector detecting a phase difference between the first clock and a clock from the candidate clocks, a phase difference controller that selects another clock from the candidate clocks, and a driver that provides transmission data synchronously with the another clock to the reader.

Abstract translation: 一种半导体器件，包括响应于从读取器经由天线接收的第一时钟，提供不同相位的候选时钟的PLL;相位差检测器，检测来自候选时钟的第一时钟和时钟之间的相位差;相位差控制器 从候选时钟中选择另一个时钟，以及向读取器提供与另一时钟同步的传输数据的驱动器。