公开(公告)号：US20240304690A1

公开(公告)日：2024-09-12

申请号：US18600700

申请日：2024-03-09

申请人： The Research Foundation for The State University of New York

发明人： Woongje SUNG ,  Sundar Isukapati

IPC分类号： H01L29/417 ,  H01L27/092 ,  H01L29/16

CPC分类号： H01L29/41783 ,  H01L27/092 ,  H01L29/1608

摘要： Embodiments herein include a substrate; a semiconductor layer formed over the substrate; a source formed in the semiconductor layer; a drain formed in the semiconductor layer, whereon the drain is disposed laterally relative to the source; and a gate.

公开(公告)号：US20240304629A1

公开(公告)日：2024-09-12

申请号：US18668988

申请日：2024-05-20

申请人： Socionext Inc.

发明人： Toshio HINO

IPC分类号： H01L27/092 ,  H01L23/528 ,  H01L27/02

CPC分类号： H01L27/0928 ,  H01L23/5286 ,  H01L27/0207

摘要： In a standard cell of a semiconductor integrated circuit device, a metal interconnect corresponding to an input node is connected to the gates of first and second transistors, and a metal interconnect corresponding to an output node is connected to the drains of third and fourth transistors. A metal interconnect corresponding to an intermediate node is connected to a gate interconnect corresponding to the gates of the third and fourth transistors through a gate contact. The gate contact is placed at a position overlapping the third transistor in planar view.

公开(公告)号：US20240304626A1

公开(公告)日：2024-09-12

申请号：US18180887

申请日：2023-03-09

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Tsung-Sheng Kang ,  Albert M. Chu ,  Tao Li ,  Chih-Chao Yang

IPC分类号： H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/528 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

摘要： A semiconductor structure including a first stacked transistor structure adjacent to a second stacked transistor structure, and a first conductive structure in direct contact with and electrically connecting a bottom gate conductor of the first stacked transistor structure and a top gate conductor of the second stacked transistor structure.

公开(公告)号：US20240304622A1

公开(公告)日：2024-09-12

申请号：US18416403

申请日：2024-01-18

申请人： Samsung Electronics Co., Ltd. ,  THE UNIVERSITY OF CHICAGO

发明人： Minsu SEOL ,  Ce LIANG ,  Jiwoong PARK ,  Kyung-Eun BYUN ,  Changhyun KIM

IPC分类号： H01L27/092 ,  H01L21/02 ,  H01L21/8256 ,  H01L29/24 ,  H01L29/66 ,  H01L29/76

CPC分类号： H01L27/092 ,  H01L21/02568 ,  H01L21/8256 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7606

摘要： Provided are a semiconductor device including a two-dimensional material and a method of manufacturing the semiconductor device. The semiconductor device may include a substrate, first and second two-dimensional material layers on the substrate and junctioned to each other in a lateral direction to form a coherent interface, a first source electrode and a first drain electrode on the first two-dimensional material layer, a first gate electrode between the first source electrode and the first drain electrode, a second source electrode and a second drain electrode on the second two-dimensional material layer, and a second gate electrode between the second source electrode and the second drain electrode.

公开(公告)号：US20240304500A1

公开(公告)日：2024-09-12

申请号：US18178665

申请日：2023-03-06

申请人： Tokyo Electron Limited

发明人： Eric Chih-Fang LIU ,  Subhadeep KAL ,  Kai-Hung YU ,  Shihsheng CHANG

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/66545

摘要： Aspects of the present disclosure provide a method for fabricating a forksheet semiconductor structure. For example, the method can include forming on a substrate a multi-layer stack including first and second semiconductor layers stacked over one another alternately, forming a cap layer over the multi-layer stack, forming a mandrel structure from the multi-layer stack and the cap layer, forming a fill material that surrounds the mandrel structure and has a top surface level with a top of the mandrel structure, partially recessing the cap layer to uncover opposite inner sidewalls of the fill material, forming sidewall spacers on the opposite inner sidewalls, directionally etching the multi-layer stack to define an insulation wall trench using the sidewall spacers as an etch mask, and forming an insulation material within the insulation wall trench to form an insulation wall that separates the multi-layer stack into insulated first and second multi-layer stacks.

公开(公告)号：US12087844B2

公开(公告)日：2024-09-10

申请号：US18356062

申请日：2023-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chih Kao ,  Hsin-Che Chiang ,  Yu-San Chien ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC分类号： H01L29/66 ,  H01L21/033 ,  H01L21/324 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/0337 ,  H01L21/324 ,  H01L21/762 ,  H01L21/76832 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

摘要： An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

公开(公告)号：US12087776B2

公开(公告)日：2024-09-10

申请号：US17586089

申请日：2022-01-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Lien Huang

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/7851

摘要： The method for forming a semiconductor device includes forming gate spacers on a substrate; forming a gate structure on the substrate and laterally between the gate spacers; forming a protective cap over the gate structure and laterally between the gate spacers; forming source/drain structures over the substrate and on opposite sides of the gate structure; depositing a dielectric layer over the protective cap, the gate spacers, and the source/drain structures; performing an etching process on the dielectric layer to form an opening exposing one of the source/drain structures, the etching process further etching a first one of the gate spacers to expose the protective cap; selectively depositing a capping material on the exposed protective cap; forming a source/drain contact in the opening.

公开(公告)号：US12087770B2

公开(公告)日：2024-09-10

申请号：US17394701

申请日：2021-08-05

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  Julien Frougier ,  Heng Wu ,  Chen Zhang ,  Kangguo Cheng

IPC分类号： H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L27/092 ,  H01L21/8221 ,  H01L21/823871 ,  H01L27/0688 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775

摘要： A complementary metal-oxide semiconductor device formed by fabricating CMOS nanosheet stacks, forming a dielectric pillar dividing the CMOS nanosheet stacks, forming CMOS FET pairs on either side of the dielectric pillar, and forming a gate contact for at least one of the FETs.

公开(公告)号：US12087587B2

公开(公告)日：2024-09-10

申请号：US17325736

申请日：2021-05-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3115 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/28088 ,  H01L21/0259 ,  H01L21/28185 ,  H01L21/28518 ,  H01L21/3115 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/0673

摘要： In some embodiments, a method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form first recesses; forming source/drain regions in the first recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; performing an aluminum treatment on the gate dielectric; depositing a first conductive material over and around the gate dielectric; performing a fluorine treatment on the first conductive material; and depositing a second conductive material over and around the first conductive material.

公开(公告)号：US20240297233A1

公开(公告)日：2024-09-05

申请号：US18116209

申请日：2023-03-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin Hsiang Tseng ,  Ming-Nung CHANG

IPC分类号： H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/42392 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a fin base on a substrate, epitaxially growing a S/D region on the fin base, depositing a dielectric layer on the S/D region, forming a contact structure on the S/D region through the dielectric layer, removing a portion of the dielectric layer to expose sidewalls of the contact structure, forming a barrier layer on the dielectric layer and to cover the exposed sidewalls of the contact structure, and forming a via structure on the contact structure through the barrier layer. The formation of the barrier layer includes depositing an insulating layer with a dielectric constant and a material density higher than a dielectric constant and a material density of the dielectric layer.