公开(公告)号：US09595971B2

公开(公告)日：2017-03-14

申请号：US15159750

申请日：2016-05-19

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Yousof Mortazavi ,  John L. Melanson ,  Aaron Brennan

IPC: H03K23/54 ,  G04F10/02 ,  H03M1/50 ,  H03K3/03 ,  H03L7/089 ,  H03L7/099 ,  H03K3/037

CPC classification number: H03K23/54 ,  G04F10/02 ,  H03K3/0315 ,  H03K3/0372 ,  H03L7/0891 ,  H03L7/0995 ,  H03M1/50

Abstract: A circuit for a divider or counter may include a frequency divider having multiple rings for dividing an input frequency to obtain an output frequency. The first and second rings may include an odd-numbered plurality of elements, such as inverters, wherein each inverter of a ring is coupled to another inverter of the ring in a circular chain. An input frequency may be input to a power supply input of inverters of the first ring. The second ring inverters may be coupled at a power supply input to output nodes of the first ring inverters, which results in the second ring operating at a divisional rate of the first frequency given by (N−1), where N is the number of inverters in the ring. The circuits may be used in frequency dividers and counters, such as in phase-locked loops (PLLs) and analog-to-digital converters (ADCs).

Abstract translation: 用于分频器或计数器的电路可以包括具有用于分频输入频率以获得输出频率的多个环的分频器。 第一和第二环可以包括奇数多个元件，例如逆变器，其中环的每个反相器以环形链耦合到环的另一反相器。 输入频率可以被输入到第一环的反相器的电源输入端。 第二环形反相器可以在电源输入处耦合到第一环形逆变器的输出节点，这导致第二环以由（N-1）给出的第一频率的分割速率操作，其中N是 逆变器在环。 这些电路可用于分频器和计数器，例如锁相环（PLL）和模数转换器（ADC）。

公开(公告)号：US09568890B1

公开(公告)日：2017-02-14

申请号：US15226323

申请日：2016-08-02

Applicant: Hongik University Industry-Academia Cooperation

Inventor： Jong Sun Kim

IPC: H03M1/50 ,  G04F10/00 ,  H03L7/089 ,  H03K5/156 ,  H03L7/18 ,  H03L7/081 ,  H03M1/56

CPC classification number: H03L7/0814 ,  H03K5/1565 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/18 ,  H03M1/56 ,  H03M2201/4233

Abstract: Disclosed is an all-digital delay locked loop circuit based on a time-to-digital converter and a control method thereof. The all-digital delay locked loop circuit includes a phase inversion locking control circuit for determining whether or not to use a phase inversion locking algorithm by detecting a phase difference between an input clock and an output clock and outputting the input clock or an inverted input clock; and a phase synchronization unit connected to an output terminal of the phase inversion locking control circuit to receive an output signal of the phase inversion locking control circuit and a control signal and perform phase synchronization, in which the phase synchronization unit includes a digital control delay line for receiving the input clock or the inverted input clock output from the phase inversion locking control circuit and reducing a phase error between the input clock and the output clock.

Abstract translation: 公开了一种基于时间 - 数字转换器的全数字延迟锁定环路电路及其控制方法。 全数字延迟锁定环电路包括相位锁定控制电路，用于通过检测输入时钟和输出时钟之间的相位差并输出输入时钟或反相输入时钟来确定是否使用相位反转锁定算法 ; 以及相位同步单元，连接到相位锁定控制电路的输出端子，以接收相位锁定控制电路的输出信号和控制信号，并执行相位同步，其中相位同步单元包括数字控制延迟线 用于接收从相位锁定控制电路输出的输入时钟或反相输入时钟，并减少输入时钟与输出时钟之间的相位误差。

公开(公告)号：US09477207B2

公开(公告)日：2016-10-25

申请号：US14654516

申请日：2013-08-22

Applicant: SANCHUAN WISDOM TECHNOLOGY CO., LTD.

Inventor： Caihua Song ,  Xianghui Zhu ,  Xianni Wang

IPC: H03M1/50 ,  G04F10/00 ,  H03K5/135 ,  H03K19/0175 ,  H03K21/02

CPC classification number: G04F10/005 ,  H03K5/135 ,  H03K19/017509 ,  H03K21/026 ,  H03M1/50

Abstract: An annular time-to-digital converter includes a pulse shaper that shapes an input start pulse and an input stop pulse to form fixed-width pulses for output. The annular time-to-digital converter also includes at least two differential comparing units that enable, during matching enabling, triggers of the differential comparing units to set setting ends to 1. A circle counter counts the number of times a pulse is propagated in a loop. A matching enabling logical device generates a matching enabling signal, and sends the generated matching enabling signal to comparing enabling ports of the differential comparing units. At least two in-loop position encoders find a position of a first matched unit according to matching signals sent by the differential comparing units. Result recording registers record the number of circles and in-loop positions when matching occurs. High resolution is realized using a differential chain, and wafer area is saved by the annular design.

Abstract translation: 环形时间 - 数字转换器包括形成输入起始脉冲和输入停止脉冲以形成用于输出的固定宽度脉冲的脉冲整形器。 环形时间 - 数字转换器还包括至少两个差分比较单元，其在匹配期间能够使差分比较单元的触发器将设定结束设置为1.循环计数器计数脉冲在 循环。 匹配使能逻辑器件产生匹配使能信号，并将生成的匹配使能信号发送到比较差分比较单元的使能端口。 至少两个循环位置编码器根据由差分比较单元发送的匹配信号找到第一匹配单元的位置。 当匹配发生时，结果记录寄存器记录圆数和循环位置。 使用差分链实现高分辨率，通过环形设计节省了晶圆面积。

公开(公告)号：US09397689B2

公开(公告)日：2016-07-19

申请号：US14551266

申请日：2014-11-24

Applicant: Intel Corporation

Inventor： Stefan Tertinek ,  Thomas Mayer ,  Peter Preyler

IPC: H03M1/50 ,  H03M1/82 ,  H03M1/00 ,  H03M1/70 ,  H03M1/66

CPC classification number: H03M1/82 ,  H03K5/06 ,  H03K5/13 ,  H03K19/00361 ,  H03L7/0812 ,  H03M1/002 ,  H03M1/661 ,  H03M1/70

Abstract: A digital to time converter is disclosed and includes a code logic and an interpolator. The code logic is configured to receive a first phase signal and a second phase signal and generate a select signal according to the first phase signal and the second phase signal. The interpolator has a bank of inverters. The interpolator is configured to generate an interpolator signal based on the select signal and an input signal.

Abstract translation: 公开了数字到时间转换器，并且包括代码逻辑和内插器。 代码逻辑被配置为接收第一相位信号和第二相位信号，并根据第一相位信号和第二相位信号产生选择信号。 内插器有一组逆变器。 内插器被配置为基于选择信号和输入信号产生内插器信号。

公开(公告)号：US09306593B2

公开(公告)日：2016-04-05

申请号：US14267790

申请日：2014-05-01

Applicant: Renesas Electronics Corporation

Inventor： Takahiro Kawano

IPC: H03M1/12 ,  H03M1/50

CPC classification number: H03M1/502

Abstract: A semiconductor device includes an analog-digital converter circuit. The analog-digital converter circuit includes a delay cell array and an encoder. The delay cell array contains n number of serially-coupled delay cells, receives a reference clock signal, and utilizes an analog input signal as the power supply voltage for the delay cells in each stage. The encoder encodes an output signal from the delay cell in each stage for the delay cell array and outputs the encoded output signal as a digital output signal. The n number of delay cells includes delay quantities weighted for each delay cell. The encoder encodes the output signal of the delay cells in each stage for the delay cell array by weighting corresponding to the number of delay cell stage.

Abstract translation: 半导体器件包括模数转换器电路。 模拟数字转换器电路包括延迟单元阵列和编码器。 延迟单元阵列包含n个串联耦合延迟单元，接收参考时钟信号，并且利用模拟输入信号作为每个级中的延迟单元的电源电压。 编码器对来自延迟单元阵列的每个级中的延迟单元的编码器进行编码，并输出编码的输出信号作为数字输出信号。 n个延迟单元包括为每个延迟单元加权的延迟量。 编码器通过对应于延迟单元级数的加权，对延迟单元阵列的每个级中的延迟单元的输出信号进行编码。

公开(公告)号：US09276600B2

公开(公告)日：2016-03-01

申请号：US14635513

申请日：2015-03-02

Applicant: DENSO CORPORATION

Inventor： Tomohito Terazawa

IPC: H03M1/50 ,  H03M1/12

CPC classification number: H03M1/12 ,  H03M1/109 ,  H03M1/129 ,  H03M1/502

Abstract: An output changing method of an A/D conversion apparatus is provided. The apparatus includes a pulse delay circuit in which delay units are connected in series, and an encoding circuit which detects the number of stages of the delay units, through which a pulse signal passes during predetermined measurement time, and generates numeric data corresponding to the number of stages. The apparatus receives an analog input signal as power supply voltage of the pulse delay circuit to perform A/D conversion for the analog input signal. The method includes determining whether or not the analog input signal is within an allowable voltage range in which the apparatus operates normally, outputting the numeric data as an A/D conversion value if the analog input signal is within the range, and outputting numeric data formed of a specified value as the A/D conversion value if the analog input signal is not within the range.

Abstract translation: 提供了一种A / D转换装置的输出改变方法。 该装置包括延迟单元串联连接的脉冲延迟电路和检测在预定测量时间期间脉冲信号通过的延迟单元的级数的编码电路，并产生与数字对应的数字数据 的阶段。 该装置接收模拟输入信号作为脉冲延迟电路的电源电压，以对模拟输入信号执行A / D转换。 该方法包括：确定模拟输入信号是否在设备正常工作的容许电压范围内，如果模拟输入信号在该范围内，则输出数字数据作为A / D转换值，并输出形成的数字数据 如果模拟输入信号不在该范围内，则为指定值作为A / D转换值。

公开(公告)号：US09176479B2

公开(公告)日：2015-11-03

申请号：US14161714

申请日：2014-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsieh-Hung Hsieh ,  Yen-Jen Chen ,  Chewn-Pu Jou

IPC: H03M1/50 ,  G04F10/00 ,  H03L7/085 ,  H03K5/159 ,  G04F10/10

CPC classification number: G04F10/005 ,  G04F10/105 ,  H03K5/159 ,  H03L7/085 ,  H03M1/50

Abstract: A time-to-digital converter (TDC) comprises a first delay line including a plurality of first delay cells connected in series, wherein each of the first delay cells include a plurality of first delay units connected in series, wherein each of the first delay units includes a tunable PMOS transistor, a first poly on oxide definition (OD) edge (PODE) transistor, and a pull-up PMOS transistor. The TDC further comprises a second delay line including a plurality of second delay cells connected in series, wherein each of the second delay cells include a plurality of second delay units connected in series, wherein each of the second delay units includes a tunable NMOS transistor, a second PODE transistor, and a pull-down NMOS transistor.

Abstract translation: 时间数字转换器（TDC）包括包括串联连接的多个第一延迟单元的第一延迟线，其中每个第一延迟单元包括串联连接的多个第一延迟单元，其中第一延迟 单元包括可调谐PMOS晶体管，第一多晶氧化物界定（OD）边缘（PODE）晶体管和上拉PMOS晶体管。 TDC还包括包括串联连接的多个第二延迟单元的第二延迟线，其中每个第二延迟单元包括串联连接的多个第二延迟单元，其中每个第二延迟单元包括可调NMOS晶体管， 第二PODE晶体管和下拉式NMOS晶体管。

公开(公告)号：US09124280B2

公开(公告)日：2015-09-01

申请号：US14305243

申请日：2014-06-16

Applicant: Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Yeomyung Kim ,  Tae Wook Kim

IPC: H03M1/50 ,  H03M1/00 ,  G04F10/00

CPC classification number: H03M1/002 ,  G04F10/005

Abstract: A time to digital converter includes: a first measurement unit measuring a time difference between a start signal and a stop signal as a first time unit by using a first delay line; a second measurement unit measuring a time difference between the stop signal and the start signal delayed by the first delay line as a second time unit by using a second delay line and a third delay line and comparing an output signal of one delay cell included in the second delay line with an output signal of at least two delay cells included in the third delay line; and an output unit outputting a final time difference between the start signal and the stop signal as a digital code on the basis of measurement results of the first measurement unit and the second measurement unit.

Abstract translation: 时间数字转换器包括：第一测量单元，通过使用第一延迟线来测量起始信号和停止信号之间的时间差作为第一时间单位; 第二测量单元，通过使用第二延迟线和第三延迟线来测量停止信号和由第一延迟线延迟的开始信号之间的时间差作为第二时间单位，并将包括在第一延迟线中的一个延迟单元的输出信号进行比较 第二延迟线，其中包括在第三延迟线中的至少两个延迟单元的输出信号; 以及输出单元，基于第一测量单元和第二测量单元的测量结果，将起始信号和停止信号之间的最后时间差作为数字代码输出。

公开(公告)号：US09081370B2

公开(公告)日：2015-07-14

申请号：US14452629

申请日：2014-08-06

Applicant: PANASONIC CORPORATION

Inventor： Shiro Dosho

IPC: H03M1/50 ,  G04F10/00 ,  G04F10/06 ,  H03K5/26

CPC classification number: G04F10/005 ,  G04F10/06 ,  H03K5/26

Abstract: A time-to-digital converter includes first and second phase distribution circuits and N time-to-digital conversion circuits. The first and second phase distribution circuits each includes a plurality of frequency dividers connected in a tree structure. The first and second phase distribution circuits each divides a signal received by the frequency dividers of root nodes into N signals. The first and second phase distribution circuits each outputs the N signals each having a different phase. The N time-to-digital conversion circuits each converts a phase difference between an i-th signal (where i is an integer from 0 to N−1) that is output from the first phase distribution circuit and another i-th signal that is output from the second phase distribution circuit into a digital value.

Abstract translation: 时间 - 数字转换器包括第一和第二相位分配电路和N个时间 - 数字转换电路。 第一和第二相分配电路各自包括以树结构连接的多个分频器。 第一和第二相位分配电路将由根节点的分频器接收的信号分成N个信号。 第一和第二相位分配电路各自输出各自具有不同相位的N个信号。 N个时间数字转换电路各自转换从第一相位分配电路输出的第i个信号（其中i是从0到N-1的整数）之间的相位差，以及另一个第i个信号 从第二相分配电路输出为数字值。

公开(公告)号：US09013635B2

公开(公告)日：2015-04-21

申请号：US13214041

申请日：2011-08-19

Applicant: Aurel A. Lazar ,  Eftychios A. Pnevmatikakis

Inventor： Aurel A. Lazar ,  Eftychios A. Pnevmatikakis

IPC: H04L27/00 ,  H03M3/00 ,  H03M1/12 ,  H03M1/66 ,  H03M1/82 ,  H03M1/50

CPC classification number: H03M3/466 ,  G06N3/049 ,  H03M1/1205 ,  H03M1/125 ,  H03M1/50 ,  H03M1/662 ,  H03M1/82 ,  H03M3/43 ,  H03M3/504

Abstract: Methods and systems for encoding and decoding signals using a Multi-input Multi-output Time Encoding Machine (TEM) and Time Decoding Machine are disclosed herein.

Abstract translation: 本文公开了使用多输入多输出时间编码机（TEM）和时间译码机对信号进行编码和解码的方法和系统。