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    Method of Forming A Self-Aligned Stack Gate Structure For Use In A Non-volatile Memory Array
    602.
    发明申请
    Method of Forming A Self-Aligned Stack Gate Structure For Use In A Non-volatile Memory Array 有权
    形成用于非易失性存储器阵列的自对准堆叠栅极结构的方法

    公开(公告)号：US20160225878A1

    公开(公告)日：2016-08-04

    申请号：US15091202

    申请日：2016-04-05

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Willem-Jan Toren ,  Xian Liu ,  Gerhard Metzger-Brueckl ,  Nhan Do ,  Stephan Wege ,  Nadia Miridi ,  Chieng-Sheng Su ,  Cecile Bernardi ,  Liz Cuevas ,  Florence Guyot ,  Yueh-Hsin Chen ,  Henry Om'mani ,  Mandana Tadayoni

    IPC: H01L29/66 ,  H01L21/28

    CPC classification number: H01L29/66545 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11568

    Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.

    Abstract translation: 用于非易失性存储器阵列的堆叠栅极结构具有半导体衬底，该半导体衬底具有多个基本上平行的间隔开的有源区，每个有源区具有沿第一方向的轴。 在垂直于第一方向的第二方向上，第一绝缘材料位于每个堆叠栅极结构之间。 每个堆叠栅极结构在有源区域上具有第二绝缘材料，在第二绝缘材料上方的电荷保持栅极，电荷保持栅极上方的第三绝缘材料以及位于第三绝缘材料上的控制栅极的第一部分。 控制栅极的第二部分在控制栅极的第一部分之上，并且与第一部分相邻并且在第二方向上延伸。 第四绝缘材料位于控制栅极的第二部分之上。

    Method Of Forming Self-Aligned Split-Gate Memory Cell Array With Metal Gates And Logic Devices
    603.
    发明申请
    Method Of Forming Self-Aligned Split-Gate Memory Cell Array With Metal Gates And Logic Devices 有权
    用金属门和逻辑器件形成自对准分离栅极存储单元阵列的方法

    公开(公告)号：US20160218110A1

    公开(公告)日：2016-07-28

    申请号：US15003659

    申请日：2016-01-21

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Jeng-Wei YANG ,  Chun-Ming CHEN ,  Man-Tang WU ,  Feng ZHOU ,  Xian LIU ,  Chien-Sheng SU ,  Nhan DO

    IPC: H01L27/115 ,  H01L21/306 ,  H01L29/66 ,  H01L21/28

    CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/30604 ,  H01L27/11536 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.

    Abstract translation: 一种通过形成间隔开的第一和第二区域形成存储器件的方法，其间具有通道区域，在沟道区域的第一部分上方形成浮栅，并与沟道区域的第一部分绝缘，形成控制栅极并与浮栅绝缘，形成 擦除栅极，并与第一区域绝缘，并且形成选通栅极，并与沟道区域的第二部分绝缘。 浮置栅极的形成包括在衬底上形成第一绝缘层，在第一绝缘层上形成第一导电层，并执行两个单独的蚀刻以形成通过第一导电层的第一和第二沟槽。 第一沟槽处的第一导电层的侧壁具有负斜率，第二沟槽处的第一导电层的侧壁是垂直的。

    Non-volatile Split Gate Memory Device And A Method Of Operating Same
    604.
    发明申请
    Non-volatile Split Gate Memory Device And A Method Of Operating Same 审中-公开
    非易失性分离存储器件及其操作方法相同

    公开(公告)号：US20160217864A1

    公开(公告)日：2016-07-28

    申请号：US15085835

    申请日：2016-03-30

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

    IPC: G11C16/24 ,  G11C16/26 ,  G11C16/04 ,  G11C16/14

    CPC classification number: G11C16/24 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

    Abstract: A non-volatile memory device that a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. A negative charge pump circuit generates a first negative voltage. A control circuit receives a command signal and generates a plurality of control signals, in response thereto and applies the first negative voltage to the word line of the unselected memory cells. During the operations of program, read or erase, a negative voltage can be applied to the word lines of the unselected memory cells.

    Abstract translation: 一种非易失性存储器件，其是第一导电类型的半导体衬底。 非易失性存储单元的阵列位于配置成多行和列的半导体衬底中。 每个存储单元包括第二导电类型的半导体衬底的表面上的第一区域和第二导电类型的半导体衬底的表面上的第二区域。 沟道区域在第一区域和第二区域之间。 字线覆盖在沟道区域的第一部分上，并且与第一区域绝缘，并且与第一区域相邻并且与第一区域几乎没有或没有重叠。 浮动栅极覆盖沟道区域的第二部分，与第一部分相邻，并与第二部分绝缘并与第二区域相邻。 耦合栅极覆盖浮栅。 位线连接到第一区域。 负电荷泵电路产生第一负电压。 控制电路接收指令信号并响应于此产生多个控制信号，并将第一负电压施加到未选择存储单元的字线。 在程序操作期间，读取或擦除时，可以对未选择的存储单元的字线施加负电压。

    Split Gate Non-volatile Flash Memory Cell Having A Silicon-Metal Floating Gate And Method Of Making Same
    608.
    发明申请
    Split Gate Non-volatile Flash Memory Cell Having A Silicon-Metal Floating Gate And Method Of Making Same 有权
    具有硅金属浮栅的分流门非易失性闪存单元及其制作方法

    公开(公告)号：US20150035040A1

    公开(公告)日：2015-02-05

    申请号：US13958483

    申请日：2013-08-02

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Jong-Won Yoo ,  Alexander Kotov ,  Yuri Tkachev ,  Chien-Sheng Su

    IPC: H01L29/788 ,  H01L29/66

    CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

    Abstract: A non-volatile memory cell includes a substrate of a first conductivity type with first and second spaced apart regions of a second conductivity type, forming a channel region therebetween. A select gate is insulated from and disposed over a first portion of the channel region which is adjacent to the first region. A floating gate is insulated from and disposed over a second portion of the channel region which is adjacent the second region. Metal material is formed in contact with the floating gate. A control gate is insulated from and disposed over the floating gate. An erase gate includes a first portion insulated from and disposed over the second region and is insulated from and disposed laterally adjacent to the floating gate, and a second portion insulated from and laterally adjacent to the control gate and partially extends over and vertically overlaps the floating gate.

    Abstract translation: 非易失性存储单元包括具有第一和第二间隔开的第二导电类型的第一导电类型的衬底，在它们之间形成沟道区。 选择栅极与与第一区域相邻的沟道区域的第一部分绝缘并布置在其上。 浮动栅极与邻近第二区域的沟道区域的第二部分绝缘并布置在其上。 金属材料形成为与浮动栅极接触。 控制栅极与浮动栅极绝缘并设置在浮动栅极上。 擦除栅极包括与第二区域绝缘并且布置在第二区域上的第一部分，并且与浮动栅极绝缘并横向邻近设置，以及与控制栅极绝缘并横向邻近控制栅极的第二部分，并且部分地延伸越过浮动 门。

    Formation Of Self-Aligned Source For Split-Gate Non-volatile Memory Cell
    609.
    发明申请
    Formation Of Self-Aligned Source For Split-Gate Non-volatile Memory Cell 有权
    用于分离门非易失性存储器单元的自对准源的形成

    公开(公告)号：US20150008451A1

    公开(公告)日：2015-01-08

    申请号：US14319893

    申请日：2014-06-30

    Applicant: SILICON STORAGE TECHNOLOGY, INC.

    Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Yueh-Hsin Chen

    IPC: H01L27/115 ,  H01L21/8234

    CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/823425 ,  H01L29/1608 ,  H01L29/42328 ,  H01L29/66825

    Abstract: A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type.

    Abstract translation: 一种具有一对导电浮动栅极的存储器件，所述导电浮动栅极具有彼此相对的内侧壁，并且设置在第一导电类型的衬底上并与其绝缘。 一对间隔开的导电控制栅极，每个导电控制栅极设置在浮动栅极中的一个上并与其绝缘，并且每个包括面向彼此的内侧壁。 一对绝缘材料的第一间隔物，沿着控制栅极内侧壁和浮动栅极延伸。 浮动门内侧壁与第一间隔件的侧表面对准。 绝缘材料的一对第二间隔物各自沿着第一间隔件中的一个并且沿着浮动栅极内侧壁中的一个延伸。 形成在衬底中的沟槽，其具有与第二间隔物的侧表面对齐的侧壁。 设置在沟槽中的硅碳。 材料注入到硅碳中，形成具有第二导电类型的第一区域。

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