公开(公告)号：US20160233641A1

公开(公告)日：2016-08-11

申请号：US14945859

申请日：2015-11-19

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Alain CHANTRE ,  Charles BAUDOT ,  Sébastien CREMER

IPC: H01S5/026 ,  H01S5/22 ,  H01S5/125

CPC classification number: H01S5/026 ,  G02B6/12004 ,  G02B6/1225 ,  G02B6/132 ,  G02B6/136 ,  H01S5/021 ,  H01S5/0264 ,  H01S5/0265 ,  H01S5/0267 ,  H01S5/0268 ,  H01S5/0422 ,  H01S5/0425 ,  H01S5/0656 ,  H01S5/1032 ,  H01S5/1035 ,  H01S5/125 ,  H01S5/22 ,  H01S5/2206

Abstract: A photonic integrated circuit includes a first insulating region encapsulating at least one metallization level, a second insulating region at least partially encapsulating a gain medium of a laser source, and a stacked structure placed between the two insulating regions. The stacked structure includes a first polycrystalline or single-crystal silicon layer, a second polycrystalline or single-crystal silicon layer, an intermediate layer optically compatible with the wavelength of the laser source and selectively etchable relative to silicon and that separates the first layer from a first portion of the second layer, and the gain medium facing at least one portion of the first layer. The first layer, the intermediate layer, and the first portion of the second layer form an assembly containing a resonant cavity and a waveguide, which are optically coupled to the gain medium, and a second portion of the second layer containing at least one other photonic component.

Abstract translation: 光子集成电路包括封装至少一个金属化水平的第一绝缘区域，至少部分地封装激光源的增益介质的第二绝缘区域和放置在两个绝缘区域之间的层叠结构。 层叠结构包括第一多晶或单晶硅层，第二多晶或单晶硅层，与激光源的波长光学兼容并且可相对于硅选择性地蚀刻的中间层，并且将第一层与 所述第二层的第一部分和所述增益介质面向所述第一层的至少一部分。 第一层，中间层和第二层的第一部分形成包含谐振腔和波导的组件，光学耦合到增益介质，第二层的第二部分包含至少一个其他光子 零件。

公开(公告)号：US09356090B2

公开(公告)日：2016-05-31

申请号：US14640705

申请日：2015-03-06

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Vincent Fiori ,  Sebastien Gallois-Garreignot ,  Denis Rideau ,  Clement Tavernier

IPC: H01L29/04 ,  H01L29/78

CPC classification number: H01L29/045 ,  H01L23/522 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A substrate includes an active region oriented along a crystallographic face (100) and limited by an insulating region. A MOS transistor includes a channel oriented longitudinally along a crystallographic direction of the type. A basic pattern made of metal and formed in the shape of a T is electrically inactive and situated over an area of the insulating region adjacent a transverse end of the channel. A horizontal branch of the T-shaped basic pattern is oriented substantially parallel to the longitudinal direction of the channel.

Abstract translation: 衬底包括沿结晶面（100）取向并被绝缘区域限制的有源区。 MOS晶体管包括沿着<110>型晶体方向纵向取向的通道。 由金属形成并形成为T形状的基本图案是电惰性的，并且位于与通道的横向端部相邻的绝缘区域的区域上。 T形基本图案的水平分支基本上平行于通道的纵向定向。

公开(公告)号：US20160118432A1

公开(公告)日：2016-04-28

申请号：US14919836

申请日：2015-10-22

Applicant: Commissariat à l'Energie Atomique et aux Energies Alternatives ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (GRENOBLE 2) SAS

Inventor： Yvon CAZAUX ,  François ROY ,  Arnaud LAFLAQUIERE ,  Marie GUILLON

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/1203 ,  H01L27/14605 ,  H01L27/14614 ,  H01L27/1463

Abstract: An image sensor arranged inside and on top of a semi-conductor substrate having a front surface and a rear surface, the sensor including a plurality of pixels, each including: a photosensitive area, a reading area, and a storage area extending between the photosensitive area and the reading area; a vertical insulated electrode including an opening of transfer between the photosensitive area and the storage area; and at least one insulation element among the following: a) a layer of an insulating material extending under the surface of the photosensitive area and of the storage area and having its front surface in contact with the rear surface of the electrode; and b) an insulating wall extending vertically in the opening, or under the opening.

Abstract translation: 布置在具有前表面和后表面的半导体衬底的内部和顶部的图像传感器，所述传感器包括多个像素，每个像素包括：感光区域，读取区域和在感光体之间延伸的存储区域 区域和阅览区域; 垂直绝缘电极，包括在感光区域和存储区域之间的转印开口; 以及以下中的至少一个绝缘元件：a）在感光区域和存储区域的表面下延伸并且其前表面与电极的后表面接触的绝缘材料层; 和b）在开口中或开口下方垂直延伸的绝缘壁。

公开(公告)号：US09269570B2

公开(公告)日：2016-02-23

申请号：US13860845

申请日：2013-04-11

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Yves Morand ,  Charles Baudot ,  Fabrice Nemouchi

IPC: H01L21/02 ,  H01L21/285

CPC classification number: H01L21/02381 ,  H01L21/28518

Abstract: A method is provided for producing a microelectronic device with plural zones made of a metal and semiconductor compound, from semiconductor zones made of different semiconductor materials, and on which a thin semiconductor layer is formed prior to the deposition of a metal layer so as to lower the nucleation barrier of the semiconductor zones when reacting with the metal layer.

Abstract translation: 提供了一种从由不同半导体材料制成的半导体区域制造具有由金属和半导体化合物制成的多个区域的微电子器件的方法，并且在沉积金属层之前在其上形成薄的半导体层以便降低 当与金属层反应时，半导体区的成核势垒。

公开(公告)号：US20160005862A1

公开(公告)日：2016-01-07

申请号：US14791713

申请日：2015-07-06

Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Shay REBOH ,  Laurent GRENOUILLET ,  Cyrille LE ROYER ,  Sylvain MAITREJEAN ,  Yves MORAND

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7847 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/26506 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/7849

Abstract: Method to strain a channel zone of a transistor of the semiconductor on insulator type transistor that makes use of an SMT stress memorisation technique in which regions located under the insulation layer of the substrate (FIG. 6) are amorphised, before the transistor gate is made.

Abstract translation: 在晶体管栅极制造之前，使用其中位于衬底（图6）的绝缘层下方的区域被非晶化的SMT应力存储技术来应变绝缘体上半导体型晶体管的晶体管的沟道区域的方法 。

公开(公告)号：US20150377962A1

公开(公告)日：2015-12-31

申请号：US14662530

申请日：2015-03-19

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Marc DAVEAU ,  Sylvain CLERC ,  Philippe ROCHE

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318502 ,  G06F11/183 ,  G06F11/267

Abstract: A method for managing operation of a logic component is provided, with the logic component including a majority vote circuit and an odd number of flip-flops equal to at least three. The method includes, following a normal operating mode of the logic component, placing a flip-flop in a test mode, and injecting a test signal into a test input of the flip-flop being tested while a logic state of the other flip-flops is frozen. A test signal output is analyzed. At the end of the test, the logic component is placed back in the normal operating mode. The majority vote circuit restores a value of the output signal from the logic component that existed prior to initiation of the test.

Abstract translation: 提供了一种用于管理逻辑部件的操作的方法，其中逻辑部件包括等于至少三个的多数投票电路和奇数触发器。 该方法包括：遵循逻辑部件的正常操作模式，将触发器置于测试模式，并将测试信号注入被测试的触发器的测试输入，而其它触发器的逻辑状态 被冻结。 分析测试信号输出。 在测试结束时，将逻辑组件放回正常操作模式。 多数投票电路恢复来自在开始测试之前存在的逻辑组件的输出信号的值。

公开(公告)号：US09165861B2

公开(公告)日：2015-10-20

申请号：US14287343

申请日：2014-05-27

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Bar ,  Simon Gousseau ,  Yann Beilliard

IPC: H01L23/427 ,  H01L23/48 ,  H01L21/768 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/3677 ,  H01L23/4275 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16235 ,  H01L2224/73204

Abstract: A method for producing at least one through-silicon via inside a substrate may include forming a cavity in the substrate from a first side of the substrate until an electrically conductive portion is emerged onto. The method may also include forming an electrically conductive layer at a bottom and on walls of the cavity, and at least partly on a first side outside the cavity. The process may further include at least partially filling the cavity with at least one phase-change material. Another aspect is directed to a three-dimensional integrated structure.

Abstract translation: 用于在衬底内部生产至少一个穿硅的方法可包括在衬底的第一侧从衬底的第一侧形成空腔，直到导电部分出现。 该方法还可以包括在空腔的底部和壁上形成导电层，并且至少部分地在空腔外部的第一侧上形成导电层。 该方法还可以包括用至少一种相变材料至少部分地填充空腔。 另一方面涉及三维综合结构。

公开(公告)号：US20150287689A1

公开(公告)日：2015-10-08

申请号：US14743072

申请日：2015-06-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent-Luc Chapelon ,  Julien Cuzzocrea

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/48

CPC classification number: H01L24/13 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/0501 ,  H01L2224/0502 ,  H01L2224/05099 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/0556 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/13657 ,  H01L2224/13684 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: An integrated circuit chip includes a substrate die and integrated circuits and a layer incorporating a front electrical interconnect network formed on a front face of the substrate die. A local electrical connection via made of an electrically conductive material is formed in a hole of the substrate die. The via is linked to a connection portion of the electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via. A local external protection layer at least partly covers the electrical connection via and the electrical connection pillar.

Abstract translation: 集成电路芯片包括衬底管芯和集成电路以及形成在衬底管芯的正面上的前部电互连网络的层。 由导电材料制成的本地电连接通孔形成在基板模具的孔中。 通孔连接到电互连网络的连接部分。 由导电材料制成的电连接柱形成在电连接通孔的后部。 局部外部保护层至少部分地覆盖电连接通孔和电连接柱。

公开(公告)号：US20150279834A1

公开(公告)日：2015-10-01

申请号：US14638292

申请日：2015-03-04

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Robert MANOUVRIER ,  Estelle Batail

IPC: H01L27/02 ,  G02B6/122

CPC classification number: G02B6/122 ,  G02B6/4275 ,  G02B6/4295 ,  H01L27/0248 ,  H01L29/74

Abstract: A thyristor may include a first optical waveguide segment in a semiconductor material, having first and second complementary longitudinal parts of opposite conductivity types configured to form a longitudinal bipolar junction therebetween. The thyristor may further include a second optical waveguide segment in a semiconductor material, adjacent the first waveguide segment and having first and second complementary longitudinal parts of opposite conductivity types configured to form a longitudinal bipolar junction therebetween. A transverse bipolar junction may be between the second longitudinal portions of the first and second waveguide segments. An electrical insulator may separate each of the first longitudinal portions from the waveguide segment adjacent thereto.

Abstract translation: 晶闸管可以包括半导体材料中的第一光波导段，其具有构造为在其间形成纵向双极结的相反导电类型的第一和第二互补纵向部分。 晶闸管可以进一步包括半导体材料中的第二光波导段，邻近第一波导段并且具有构造成在其间形成纵向双极结的相反导电类型的第一和第二互补纵向部分。 横向双极结可以在第一和第二波导段的第二纵向部分之间。 电绝缘体可以将每个第一纵向部分与与其相邻的波导段分开。

公开(公告)号：US20150277038A1

公开(公告)日：2015-10-01

申请号：US14656981

申请日：2015-03-13

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Robert MANOUVRIER ,  Patrick LEMAITRE ,  Jean-Francois CARPENTIER

IPC: G02B6/12 ,  G02B6/13

CPC classification number: G02B6/12 ,  G02B6/122 ,  G02B6/13 ,  G02B6/132 ,  H01L29/74

Abstract: An optical waveguide in a semiconductor material, may include, between two adjacent portions of the waveguide, a plurality of parallel strips of alternating conductivity types forming a plurality of opposing bipolar junctions between the two adjacent portions.

Abstract translation: 在半导体材料中的光波导可以包括在波导的两个相邻部分之间的多个交替导电类型的平行条带，在两个相邻部分之间形成多个相对的双极结。