公开(公告)号：US20190206879A1

公开(公告)日：2019-07-04

申请号：US15884063

申请日：2018-01-30

Applicant: United Microelectronics Corp.

Inventor： Chun-Hsien Huang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chang-Hung Chen ,  Shu-Ru Wang ,  Wei-Chi Lee ,  Chun-Yen Tseng

IPC: H01L27/11 ,  H01L27/092 ,  G11C11/41 ,  H01L23/522 ,  H01L27/02

Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure has a first line terminal. The second circuit structure has a second line terminal. The first line terminal and the second line terminal are formed in a first circuit layer but separated by a gap. A conductive structure is forming in a second circuit layer above or below the first circuit layer, to electrically connect the first line terminal and the second line terminal.

公开(公告)号：US20190206874A1

公开(公告)日：2019-07-04

申请号：US16294934

申请日：2019-03-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10805 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: A semiconductor memory device and a manufacturing method thereof are provided. At least one bit line structure including a first metal layer, a bit line capping layer, and a first silicon layer located between the first metal layer and the bit line capping layer is formed on a semiconductor substrate. A bit line contact opening penetrating the bit line capping layer is formed for exposing a part of the first silicon layer. A first metal silicide layer is formed on the first silicon layer exposed by the bit line contact opening. A bit line contact structure is formed in the bit line contact opening and contacts the first metal silicide layer for being electrically connected to the bit line structure. The first silicon layer in the bit line structure may be used to protect the first metal layer from being damaged by the process of forming the metal silicide layer.

公开(公告)号：US20190206459A1

公开(公告)日：2019-07-04

申请号：US15992130

申请日：2018-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Yu Lu ,  Chun-Hsien Huang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Shou-Sian Chen ,  Koji Nii ,  Yuichiro Ishii

IPC: G11C8/16 ,  G11C8/08 ,  G11C7/12 ,  G11C11/412 ,  H01L27/11

CPC classification number: G11C8/16 ,  G11C5/025 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C8/14 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L27/11

Abstract: A dual port static random access memory (DPSRAM) cell includes a first power line, a first bit line and a second bit line. The first power line is disposed between a first word line and a second word line. The first bit line is disposed between the first word line and the first power line. The second bit line is disposed between the second word line and the first power line.

公开(公告)号：US10340349B2

公开(公告)日：2019-07-02

申请号：US15799692

申请日：2017-10-31

Applicant: United Microelectronics Corp.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L49/02 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11521

Abstract: A method of forming a semiconductor structure is disclosed. A substrate having a first area and a second area is provided, wherein a first surface of the first area is lower than a second surface of the second area. A first insulating layer, a first gate, a first dielectric layer and a first dummy gate are sequentially formed on the first surface of the first area. A second dielectric layer and a second dummy gate are formed on the second surface of the second area. An inter-layer dielectric layer is formed around the first gate, the first dummy gate and the second dummy gate. The first dummy gate and the second dummy gate are removed, so as to form a first trench and a second trench in the inter-layer dielectric layer. A second gate and a third gate are filled respectively in the first trench and the second trench.

公开(公告)号：US10332888B2

公开(公告)日：2019-06-25

申请号：US15810145

申请日：2017-11-13

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chien Liu ,  Chia-Lung Chang ,  Han-Yung Tsai ,  Tzu-Chin Wu

IPC: H01L21/285 ,  H01L27/108

Abstract: A method of manufacturing memory devices is provided in the present invention. The method includes the steps of providing a substrate with multiple capacitors, wherein the capacitor includes a lower electrode layer, an insulating layer and an upper electrode layer and a top plate, forming a tungsten layer on the upper electrode, performing a nitriding plasma treatment to the tungsten layer to form a tungsten nitride layer, and forming a pre-metal dielectric layer on the tungsten nitride layer.

公开(公告)号：US20190189618A1

公开(公告)日：2019-06-20

申请号：US15867615

申请日：2018-01-10

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hong-Ru Liu ,  Kuei-Hsuan Yu

IPC: H01L27/108

CPC classification number: H01L27/10823 ,  H01L21/3065 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/42376 ,  H01L29/7827

Abstract: A memory cell includes a curved gate channel transistor, a buried bit line, a word line and a capacitor. The curved gate channel transistor has a first doped region located in a substrate, a second doped region and a third doped region located on the substrate, wherein the second doped region is directly on the first doped region and the third doped region is right next to the second doped region, thereby constituting a curved gate channel. The buried bit line is located below the first doped region. The word line covers the second doped region. The capacitor is located above the curved gate channel transistor and in electrical contact with the third doped region. The present invention also provides a memory cell having a vertical gate channel transistor, and the vertical gate channel has current flowing downward.

公开(公告)号：US20190187674A1

公开(公告)日：2019-06-20

申请号：US16285067

申请日：2019-02-25

Applicant: United Microelectronics Corp.

Inventor： Feng-Chi Chung ,  Ching-Hsing Hsieh ,  Yi-Chun Lin ,  Chien-Chuan Yu

IPC: G05B23/02

CPC classification number: G05B23/0221 ,  G03F7/70608 ,  G03F7/70616

Abstract: A virtual metrology system at least includes a process apparatus including a set of process data, the process apparatus producing a workpiece according to the set of process data. A virtual metrology server is configured to gather the set of process data, cluster the set of process data to obtain data clusters, and compare the data clusters with patterns. If the data clusters meet the patterns corresponding to the data clusters, performing a corresponding maintenance, repair, and overhaul step on the process apparatus.

公开(公告)号：US20190172831A1

公开(公告)日：2019-06-06

申请号：US15857642

申请日：2017-12-29

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Yu-Cheng Tung ,  Fu-Che Lee

IPC: H01L27/108

Abstract: A layout of semiconductor structure includes plural patterns arranged along a first direction to form plural columns, with each pattern spaced from each other. A region is defined by the patterns, and which includes a first edge and a second edge, with the first edge extended along the first direction, and the second edge extended along a second direction different from the first direction and being serrated. The second edge includes plural fragments, with each fragment being defined by at least two patterns. The present invention also provided a semiconductor device and a method of forming the same.

公开(公告)号：US20190172722A1

公开(公告)日：2019-06-06

申请号：US16158316

申请日：2018-10-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Wei-Hsin Liu ,  Ying-Chih Lin ,  Jui-Min Lee ,  Gang-Yi Lin ,  Fu-Che Lee

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/033 ,  H01L27/105

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/1052

Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a target layer is provided, and a mask structure is formed on the target layer, with the mask structure including a first mask layer a sacrificial layer and a second mask layer. The first mask layer and the second mask layer include the same material but in different containing ratio. Next, the second mask layer and the sacrificial layer are patterned, to form a plurality of mandrels. Then, a plurality of spacer patterns are formed to surround the mandrels, and then transferred into the first mask layer to form a plurality of opening not penetrating the first mask layer. Finally, the first mask layer is used as a mask to etch the target layer, to form a plurality of target patterns.

公开(公告)号：US10312249B2

公开(公告)日：2019-06-04

申请号：US15808019

申请日：2017-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Chuan Sun ,  Wei Ta ,  Wang Xiang

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/266 ,  H01L29/788

Abstract: A method for forming a semiconductor device is provided, including providing a substrate having a first area comprising first semiconductor structures and a second area, wherein one of the first semiconductor structures comprises a memory gate made of a first polysilicon layer, and a second semiconductor structure comprises a second polysilicon layer disposed within the second area on the substrate; forming an organic material layer on the first semiconductor structures within the first area and on the second polysilicon layer within the second area; and patterning the organic material layer to form a patterned organic material layer, and the organic material layer exposing the memory gates of the first semiconductor structures, wherein a first pre-determined region and a second pre-determined region at the substrate are covered by the patterned organic material layer.