公开(公告)号：US20130292823A1

公开(公告)日：2013-11-07

申请号：US13869072

申请日：2013-04-24

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Laurent-Luc Chapelon

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/5384 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/80141 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81141 ,  H01L2224/81815 ,  H01L2224/9201 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20754 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.

公开(公告)号：US20130270662A1

公开(公告)日：2013-10-17

申请号：US13858389

申请日：2013-04-08

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： François Roy ,  Vincent Fiori

IPC: H01L31/18 ,  H01L31/02

CPC classification number: H01L31/18 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14687 ,  H01L27/1469 ,  H01L31/02 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing an image sensor, including the steps of: forming elementary structures of an image sensor on the first surface of a semiconductor substrate; installing a handle on the first surface; defining trenches in the handle, the trenches forming a pattern in the handle; and installing, on a hollow curved substrate, the obtained device on the free surface side of the handle, the pattern being selected according to the shape of the support surface.

Abstract translation: 一种用于制造图像传感器的方法，包括以下步骤：在半导体衬底的第一表面上形成图像传感器的元件结构; 在第一个表面上安装手柄; 在手柄中限定沟槽，沟槽在手柄中形成图案; 并且在空心弯曲基板上将所获得的装置安装在手柄的自由表面侧上，根据支撑表面的形状选择图案。

公开(公告)号：US20130181220A1

公开(公告)日：2013-07-18

申请号：US13624214

申请日：2012-09-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Rachid Taibi ,  Cedrick Chappaz ,  Lea Di Cioccio ,  Laurent-Luc Chapelon

IPC: H01L21/66

CPC classification number: H01L25/0657 ,  H01L22/12 ,  H01L22/14 ,  H01L27/0688 ,  H01L2224/48463 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06596

Abstract: A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated circuits and opening onto two locations respectively in electrical contact with the two metallic lines. The cavities may be sized to place a measuring apparatus at the bottom of the cavities, and in electrical contact with the two locations.

公开(公告)号：US20130099329A1

公开(公告)日：2013-04-25

申请号：US13659771

申请日：2012-10-24

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Mickael Gros-Jean ,  Clement Gaumer ,  Emmanuel Bayard Perrin

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L21/76232 ,  H01L21/28229 ,  H01L21/823481 ,  H01L29/513 ,  H01L29/518

Abstract: A method for defining an insulator in a semiconductor substrate includes forming a trench in the substrate, forming in the trench an insulating material having its upper surface arranged above the surface of the substrate, and forming a diffusion barrier layer in a portion of the insulating material located above the surface of the semiconductor substrate. Such insulators can be used, for example, to insulate and delineate electronic components or portions of components formed in the substrate.

Abstract translation: 一种用于在半导体衬底中限定绝缘体的方法包括在衬底中形成沟槽，在沟槽中形成其上表面布置在衬底表面上方的绝缘材料，并在绝缘材料的一部分中形成扩散阻挡层 位于半导体衬底的表面上方。 这样的绝缘体可以用于例如绝缘并描绘形成在基板中的电子部件或部件。

公开(公告)号：US12302011B2

公开(公告)日：2025-05-13

申请号：US17883764

申请日：2022-08-09

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Frederic Lalanne ,  Pierre Malinge

IPC: H04N25/77 ,  G01J1/44 ,  H04N5/33 ,  H04N25/42 ,  H04N25/75

Abstract: A photosensitive sensor is capable of operating in a global shutter mode and in a rolling shutter mode. The sensor includes at least one pixel with a photosensitive region configured to photogenerate charges. A first transfer gate is configured to transfer photogenerated charges from the photosensitive region to a transfer node. A source-follower transistor is configured to transmit a reading signal to a read node, in the global shutter mode, in a manner controlled by a potential of the photogenerated charges on the transfer node. A second transfer gate is configured to transfer the photogenerated charges from the photosensitive region to the read node in the rolling shutter mode.

公开(公告)号：US12295272B2

公开(公告)日：2025-05-06

申请号：US17847016

申请日：2022-06-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent Favennec ,  Fausto Piazza

IPC: H10N70/20 ,  H01L23/522 ,  H10B63/10 ,  H10N70/00

Abstract: A method for making a phase change memory includes a step of forming an array of phase change memory cells, with each cell being separated from neighboring cells in the same line of the array and from neighboring cells in the same column of the array, by the same first distance. The method further includes a step of etching one memory cell out of N, with N being at least equal to 2, in each line or each column.

公开(公告)号：US20250126877A1

公开(公告)日：2025-04-17

申请号：US18986599

申请日：2024-12-18

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierpaolo MONGE ROFFARELLO ,  Isabella MICA ,  Didier DUTARTRE ,  Alexandra ABBADIE

IPC: H10D84/03 ,  H01L21/02 ,  H01L21/324 ,  H01L21/763 ,  H10D84/01 ,  H10D84/40

Abstract: A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.

公开(公告)号：US12232435B2

公开(公告)日：2025-02-18

申请号：US18130184

申请日：2023-04-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

公开(公告)号：US20250044627A1

公开(公告)日：2025-02-06

申请号：US18919835

申请日：2024-10-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sébastien Cremer

IPC: G02F1/1333 ,  G02B6/13 ,  G02F1/01

Abstract: A method includes forming a layer made of a first insulating material on a first layer made of a second insulating material that covers a support, defining a waveguide made of the first material in the layer of the first material, covering the waveguide made of the first material with a second layer of the second material, planarizing an upper surface of the second layer of the second material, and forming a single-crystal silicon layer over the second layer.

公开(公告)号：US12218163B2

公开(公告)日：2025-02-04

申请号：US18591950

申请日：2024-02-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mickael Fourel ,  Laurent-Luc Chapelon

IPC: H01L27/146 ,  G02B1/10 ,  G02B1/14 ,  G02B3/00

Abstract: An image acquisition device includes an array of color filters and an array of microlenses over the array of color filters. At least one layer made from an inorganic dielectric material is formed between the array of color filters and the array of microlenses.