公开(公告)号：US10418332B2

公开(公告)日：2019-09-17

申请号：US15456972

申请日：2017-03-13

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Goo Lee ,  KyungMoon Kim ,  SooSan Park ,  KeoChang Lee

IPC: H01L23/552 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00 ,  H01L25/16 ,  H01L25/065 ,  H01L23/538 ,  H01L23/16 ,  H01L23/31

Abstract: A semiconductor device has a partition fence disposed between a first attach area and a second attach area on a substrate. A first electrical component is disposed over the first attach area. A second electrical component is disposed over the second attach area. The partition fence extends above and along a length of the first electrical component and second electrical component. An encapsulant is deposited over the substrate, first electrical component, second electrical component, and partition fence. A portion of the encapsulant is removed to expose a surface of the partition fence and planarizing the encapsulant. A shielding layer is formed over the encapsulant and in contact with the surface of the partition fence. The combination of the partition fence and shielding layer compartmentalize the first electrical component and second electrical component for physical and electrical isolation to reduce the influence of EMI, RFI, and other inter-device interference.

公开(公告)号：US10388637B2

公开(公告)日：2019-08-20

申请号：US15830644

申请日：2017-12-04

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： OhHan Kim ,  DeokKyung Yang ,  HunTeak Lee ,  InSang Yoon ,  Il Kwon Shim

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/13

Abstract: A semiconductor device has a first substrate. A first semiconductor component and second semiconductor component are disposed on the first substrate. In some embodiments, a recess is formed in the first substrate, and the first semiconductor component is disposed on the recess of the first substrate. A second substrate has an opening formed through the second substrate. A third semiconductor component is disposed on the second substrate. The second substrate is disposed over the first substrate and second semiconductor component. The first semiconductor component extends through the opening. An encapsulant is deposited over the first substrate and second substrate.

公开(公告)号：US10388626B2

公开(公告)日：2019-08-20

申请号：US12947414

申请日：2010-11-16

Applicant: Rajendra D. Pendse

Inventor： Rajendra D. Pendse

IPC: H01L23/52 ,  H01L23/538 ,  H05K3/34 ,  H05K3/24 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H05K3/32

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps or interconnect structures formed over an active surface of the die. The bumps can have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. A plurality of conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites under pressure or reflow temperature so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the die and substrate. The masking layer can form a dam to block the encapsulant from extending beyond the semiconductor die. Asperities can be formed over the interconnect sites or bumps.

公开(公告)号：US10319684B2

公开(公告)日：2019-06-11

申请号：US15485085

申请日：2017-04-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： InSang Yoon ,  SeungYong Chai ,  SoYeon Park

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552

Abstract: A semiconductor device has a first conductive layer and a second conductive layer. A first portion of the first conductive layer is aligned with a first portion of the second conductive layer. An insulating layer is deposited over the first conductive layer and second conductive layer. A third conductive layer includes a first portion of the third conductive layer vertically aligned with the first portion of the first conductive layer and the first portion of the second conductive layer. An electrical component is disposed over the first conductive layer and second conductive layer. An encapsulant is deposited over the first conductive layer, second conductive layer, and electrical component. A cut is made through the encapsulant, first conductive layer, and second conductive layer. A fourth conductive layer is deposited over side surfaces of the first conductive layer, second conductive layer, and encapsulant.

公开(公告)号：US10242887B2

公开(公告)日：2019-03-26

申请号：US15674247

申请日：2017-08-10

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device includes a carrier and a plurality of semiconductor die disposed over the carrier. An encapsulant is deposited over the semiconductor die. A composite layer is formed over the encapsulant to form a panel. The carrier is removed. A conductive layer is formed over the panel. An insulating layer is formed over the conductive layer. The carrier includes a glass layer, a second composite layer formed over the glass layer, and an interface layer formed over the glass layer. The composite layer and encapsulant are selected to tune a coefficient of thermal expansion of the panel. The panel includes panel blocks comprising an opening separating the panel blocks. The encapsulant or insulating material is deposited in the opening. A plurality of support members are disposed around the panel blocks. An interconnect structure is formed over the conductive layer.

公开(公告)号：US20190088603A1

公开(公告)日：2019-03-21

申请号：US16184134

申请日：2018-11-08

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Pandi Chelvam Marimuthu ,  Andy Chang Bum Yong ,  Aung Kyaw Oo ,  Yaojian Lin

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/522 ,  H01L23/552 ,  H01L23/538 ,  H01L21/48 ,  H01L23/528

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.

公开(公告)号：US20190047845A1

公开(公告)日：2019-02-14

申请号：US16169817

申请日：2018-10-24

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Won Kyoung Choi ,  Kang Chen ,  Ivan Micallef

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81B2207/092 ,  B81B2207/098 ,  B81C1/0023 ,  B81C1/00301 ,  B81C1/00904 ,  B81C2203/0792 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/16 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/13091 ,  H01L2924/15 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

公开(公告)号：US10177010B2

公开(公告)日：2019-01-08

申请号：US15235008

申请日：2016-08-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Hin Hwa Goh ,  Il Kwon Shim

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L23/13 ,  H01L23/538

Abstract: A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over the second surface of the substrate. An indentation is formed in a sidewall of the substrate. An opening is formed through the substrate. An encapsulant is deposited in the opening. An insulating layer is formed over second surface of the substrate. A dummy opening is formed in the insulating layer. A semiconductor die is disposed adjacent to the substrate. An encapsulant is deposited over the semiconductor die and substrate. The first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.

公开(公告)号：US10163815B2

公开(公告)日：2018-12-25

申请号：US14090036

申请日：2013-11-26

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Xia Feng ,  Kang Chen ,  Jianmin Fang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/58

Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die.

公开(公告)号：US10141222B2

公开(公告)日：2018-11-27

申请号：US14566870

申请日：2014-12-11

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu

IPC: H01L21/768 ,  H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H05K1/18

Abstract: A semiconductor device has a semiconductor die mounted over the carrier. An encapsulant is deposited over the carrier and semiconductor die. The carrier is removed. A first interconnect structure is formed over the encapsulant and a first surface of the die. A second interconnect structure is formed over the encapsulant and a second surface of the die. A first protective layer is formed over the first interconnect structure and second protective layer is formed over the second interconnect structure prior to forming the vias. A plurality of vias is formed through the second interconnect structure, encapsulant, and first interconnect structure. A first conductive layer is formed in the vias to electrically connect the first interconnect structure and second interconnect structure. An insulating layer is formed over the first interconnect structure and second interconnect structure and into the vias. A discrete semiconductor component can be mounted to the first interconnect structure.