公开(公告)号：US20240334340A1

公开(公告)日：2024-10-03

申请号：US18128805

申请日：2023-03-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Paul Blinzer ,  Chirag Nitinkumar Dhruv ,  Ranjeet Kumar ,  Gia Tung Phan ,  Ashish Jain

IPC: H04W52/02

CPC classification number: H04W52/029 ,  H04W52/0274

Abstract: An apparatus and method for efficiently performing power management for increasing reliable wireless signal transfer performed by mobile computing devices. In various implementations, a computing system includes a network interface and multiple components for processing tasks. The network interface sends, to at least a given component of the multiple components, an indication specifying the corresponding operating frequency ranges used by one or more radio modules used for wireless communication with an access point. The given component determines whether an operating clock frequency of the given component overlaps any of the received operating frequency ranges and associated harmonic frequencies. If so, then the given component changes the operating clock frequency to a frequency that does not overlap any of the received operating frequency ranges and associated harmonic frequencies.

公开(公告)号：US20240330214A1

公开(公告)日：2024-10-03

申请号：US18191207

申请日：2023-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lianji Cheng ,  Xiao Han ,  Qing Li

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: An apparatus includes logic circuitry, such as an interrupt controller, that serially arbitrates among a plurality of incoming interrupt requests for a target device and produces a selected incoming interrupt request. The logic generates a message signaled interrupt (MSI) message for the target device based on the selected incoming interrupt request using a plurality of linked lookup tables, such as a hierarchy of LUTs that include data used to generate the MSI message. Associated methods are also presented.

公开(公告)号：US20240330196A1

公开(公告)日：2024-10-03

申请号：US18388602

申请日：2023-11-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Skyler J. SALEH ,  Samuel NAFFZIGER ,  Milind S. BHAGAVAT ,  Rahul AGARWAL

IPC: G06F12/0897 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F12/0897 ,  G06F13/1668 ,  G06F13/4027 ,  G06F2212/1024

Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink. The passive crosslink is a passive interposer die dedicated for inter-chiplet communications and partitions systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

公开(公告)号：US20240329998A1

公开(公告)日：2024-10-03

申请号：US18619392

申请日：2024-03-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Bin He ,  Michael J. Mantor ,  Brian D. Emberling

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3802 ,  G06F9/3001 ,  G06F9/30098 ,  G06F9/3867

Abstract: An apparatus and method for efficiently processing multiplication and accumulate operations for matrices in applications. In various implementations, a computing system includes a parallel data processing circuit and a memory. The memory stores the instructions (or translated commands) of a parallel data application. The circuitry of the parallel data processing circuit performs a matrix multiplication operation using source operands accessed only once from a vector register file and multiple instantiations of a vector processing circuit capable of performing multiple matrix multiplication operations corresponding to multiple different types of instructions. The multiplier circuit and the adder circuit of the vector processing circuit perform each of the fused multiply add (FMA) operation and the dot product (inner product) operation without independent, dedicated execution pipelines with one execution pipeline for the FMA operation and the other separate execution pipeline for the dot product operation.

公开(公告)号：US12105952B2

公开(公告)日：2024-10-01

申请号：US17957469

申请日：2022-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Vydhyanathan Kalyanasundharam

IPC: G06F3/06

CPC classification number: G06F3/0607 ,  G06F3/0629 ,  G06F3/067

Abstract: Systems, methods, and techniques are provided for a fabric addressable memory. A memory access request is received from a host computing device attached via one edge port of one or more interconnect switches, the memory access request directed to a destination segment of a physical fabric memory block that is allocated in local physical memory of the host computing device. The edge port accesses a stored mapping between segments of the physical fabric memory block and one or more destination port identifiers that are each associated with a respective edge port of the fabric addressable memory. The memory access request is routed by the one edge port to a destination edge port based on the stored mapping.

公开(公告)号：US20240324247A1

公开(公告)日：2024-09-26

申请号：US18474111

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Samuel Naffziger ,  William George En ,  John Wuu

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L25/18 ,  H01L25/50 ,  H01L23/5286 ,  H01L24/06 ,  H01L2224/06181 ,  H01L2224/08145

Abstract: A method for die pair partitioning can include providing a circuit die that has a metal stack and that includes a majority of logic transistors of an integrated circuit. The method can also include providing one or more additional circuit die that have one or more additional metal stacks of which at least one is connected to the metal stack of the circuit die and a majority of static random access memory and analog devices of the integrated circuit. The method can further include connecting at least one of the one or more additional metal stacks to the metal stack of the circuit die. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240321827A1

公开(公告)日：2024-09-26

申请号：US18474158

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc. ,  Xilinx, Inc.

Inventor： Omar Zia ,  Thomas D Burd ,  Kevin Gillespie ,  Samuel Naffziger ,  Richard Schultz ,  Raja Swaminathan ,  Srividhya Venkataraman ,  Yan Wang ,  John Wuu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L23/36 ,  H01L23/481 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A method for circuit die stacking can include providing a first circuit die having a first metal stack, wherein the first circuit die corresponds to a primary thermal source of an integrated circuit including the first circuit die. The method can additionally include providing a second circuit die of the integrated circuit, wherein the second circuit die has a second metal stack and is configured for connection to at least one of a package substrate or an additional die. The method can also include connecting the first metal stack to the second metal stack. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240321668A1

公开(公告)日：2024-09-26

申请号：US18474138

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc. ,  Xilinx, Inc.

Inventor： Thomas D. Burd ,  Gabriel H. Loh ,  John Wuu ,  Kevin Gillespie ,  Raja Swaminathan ,  Richard Schultz ,  Samuel Naffziger ,  Srividhya Venkataraman ,  Yan Wang

IPC: H01L23/34 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/34 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/80 ,  H01L25/0652 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/16225 ,  H01L2224/32221 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1437

Abstract: A method for die pair partitioning can include providing a first circuit die having a first metal stack. The method can additionally include positioning a second circuit die having a second metal stack in a manner that places a temperature sensor in a transistor layer of the second circuit die in planar proximity to at least one hot spot located in an additional transistor layer of the first circuit die. The method can also include connecting the first metal stack of the first circuit die to the second metal stack of the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240319964A1

公开(公告)日：2024-09-26

申请号：US18126107

申请日：2023-03-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Onur Kayiran ,  Lee Evan Eisen ,  Michael Estlick ,  Jay Fleischman ,  Matthew R. Poremba ,  Gabriel H. Loh

IPC: G06F7/503

CPC classification number: G06F7/503

Abstract: A processor includes one or more processor cores configured to perform accumulate top (ACCT) and accumulate bottom (ACCB) instructions. To perform such instructions, at least one processor core of the processor includes an ACCT data path that adds a first portion of a block of data to a first lane of a set of lanes of a top accumulator and adds a carry-out bit to a second lane of the set of lanes of the top accumulator. Further, the at least one processor core includes an ACCB data path that adds a second portion of the block of data to a first lane of a set of lanes of a bottom accumulator and adds a carry-out bit to a second lane of the set of lanes of the bottom accumulator.

公开(公告)号：US20240319781A1

公开(公告)日：2024-09-26

申请号：US18189993

申请日：2023-03-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Gia Tung Phan ,  Randall Brown ,  Ashish Jain

IPC: G06F1/3234 ,  G06F1/3228 ,  G06F1/3287

CPC classification number: G06F1/3275 ,  G06F1/3228 ,  G06F1/3287

Abstract: An apparatus and method for efficient power management of multiple integrated circuits. In various implementations, a computing system includes an integrated circuit with a security processor. The security processor determines the integrated circuit transitions to an active state from a sleep state that is not intended to maintain configuration information to return to the active state without restarting an operating system. In the sleep state, multiple components of the integrated circuit have a power supply reference level turned off, which provides low power consumption for the integrated circuit. The security processor performs the bootup operation using information stored in persistent on-chip memory. By not using information stored in off-chip memory, the security processor reduces the latency of the transition. The persistent on-chip memory utilizes synchronous random-access memory that receives a standby power supply reference level that continually supplies a voltage magnitude by not being turned off.