公开(公告)号：US20090004809A1

公开(公告)日：2009-01-01

申请号：US11970555

申请日：2008-01-08

申请人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  Keith Edward Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert Mark Rassel ,  Anthony Kendall Stamper ,  Kunal Vaed

发明人： Anil Kumar Chinthakindi ,  Douglas Duane Coolbaugh ,  Keith Edward Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert Mark Rassel ,  Anthony Kendall Stamper ,  Kunal Vaed

IPC分类号： H01L21/20

CPC分类号： H01L28/40

摘要： A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by side wall spacers.

摘要翻译： 在具有顶表面并且包括形成在从浅沟槽隔离（STI）区域中选择的表面中的区域和具有与半导体衬底共面的外表面的掺杂阱的半导体衬底上形成MIM电容器。 电容器底板是形成在半导体衬底中的STI区域上的下电极或由可能具有硅化物表面的在半导体衬底的顶表面中形成的掺杂阱形成的下电极。 电容器HiK电介质层形成在下板上或上。 在电容器下板上方的HiK电介质层上形成电容器第二板。 可以在第二板的上方形成具有顶板的双电容器结构，其中通过侧壁间隔件连接到被第二板保护的下板的通孔。

公开(公告)号：US20080232025A1

公开(公告)日：2008-09-25

申请号：US12133425

申请日：2008-06-05

申请人： Douglas Duane Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert Mark Rassel

发明人： Douglas Duane Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert Mark Rassel

IPC分类号： H01G4/228

CPC分类号： H01L28/60

摘要： A MIM capacitor device and method of making the device. The device includes an upper plate comprising one or more electrically conductive layers, a dielectric block comprising one or more dielectric layers, a lower plate comprising one or more electrically conductive layer; and a spreader plate comprising one or more electrically conductive layers.

摘要翻译： 一种MIM电容器及其制造方法。 该装置包括一个包括一个或多个导电层的上板，一个包括一个或多个电介质层的介质块，包括一个或多个导电层的下板; 以及包括一个或多个导电层的扩展板。

公开(公告)号：US07427550B2

公开(公告)日：2008-09-23

申请号：US11427457

申请日：2006-06-29

申请人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L21/20

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

摘要翻译： 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

公开(公告)号：US20080158771A1

公开(公告)日：2008-07-03

申请号：US11616955

申请日：2006-12-28

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Richard P. Volant

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Richard P. Volant

IPC分类号： H01G4/30 ,  H01G9/00

CPC分类号： H01G4/33 ,  H01G4/005 ,  H01L23/5223 ,  H01L28/90 ,  H01L2924/0002 ,  Y10T29/417 ,  H01L2924/00

摘要： A method of forming a metal-insulator-metal (MIM) capacitor includes forming a first planar dielectric layer with a first metallization layer therein; forming a first passivation layer on top thereof; forming a planar conductive layer above the first passivation layer; patterning and selectively removing the conductive layer up to the first passivation layer in designated areas to form a set of conductive features; patterning and conformally coating the set of conductive features and the exposed first passivation layer with a high strength dielectric coating; disposing a second dielectric layer above the first passivation layer and enclosing the set of conductive features; patterning and selectively removing portions of the second substrate to form channels and trenches; performing a dual-Damascene process to form a second metallization layer in the trenches and channels and to form an upper conductive surface above the high strength dielectric coating.

摘要翻译： 形成金属 - 绝缘体 - 金属（MIM）电容器的方法包括在其中形成第一平面介质层和第一金属化层; 在其顶部形成第一钝化层; 在所述第一钝化层上形成平面导电层; 在指定区域中图案化和选择性地去除导电层直到第一钝化层以形成一组导电特征; 用高强度电介质涂层构图并保形地涂覆该组导电特征和暴露的第一钝化层; 在所述第一钝化层上设置第二电介质层并且包围所述一组导电特征; 图案化和选择性地去除第二衬底的部分以形成沟道和沟槽; 执行双镶嵌工艺以在沟槽和通道中形成第二金属化层，并在高强度电介质涂层上形成上导电表面。

公开(公告)号：US07394110B2

公开(公告)日：2008-07-01

申请号：US11307404

申请日：2006-02-06

申请人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Kevin S. Petrarca ,  Anthony K. Stamper ,  Richard P. Volant

发明人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Kevin S. Petrarca ,  Anthony K. Stamper ,  Richard P. Volant

IPC分类号： H01L23/62

CPC分类号： H01L28/20 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.

摘要翻译： 公开了避免半导体器件小型化的问题的电阻器及相关方法。 在一个实施例中，电阻器包括在半导体器件的至少一个金属层内垂直延伸的平面电阻器材料。 在另一个实施例中，电阻器包括在半导体器件的第一接合焊盘和第二接合焊盘之间延伸的电阻材料层。 这两个实施方案可以单独使用或一起使用。 还公开了用于产生电阻器的相关方法。

公开(公告)号：US07361993B2

公开(公告)日：2008-04-22

申请号：US10908346

申请日：2005-05-09

申请人： Douglas D. Coolbaugh ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

发明人： Douglas D. Coolbaugh ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

IPC分类号： H01L29/40

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05022 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05552

摘要： Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.

摘要翻译： 端子焊盘和制造端子焊盘的方法。 所述方法包括在由包括扩散阻挡层的多个电介质层组成的钝化层的内部或与其重叠的导电焊盘下方形成导电扩散阻挡层。 所述方法包括减法地形成端子焊盘或通过镶嵌工艺。

公开(公告)号：US07145218B2

公开(公告)日：2006-12-05

申请号：US10709692

申请日：2004-05-24

申请人： Ebenezer E. Eshun

发明人： Ebenezer E. Eshun

IPC分类号： H01L29/00

CPC分类号： H01L23/5228 ,  H01C1/142 ,  H01C7/006 ,  H01L27/016 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention relates to integration of a thin-film resistor in a wiring level, such as, for example, an aluminum back-end-of-line (BEOL) technology. The thin-film resistor is formed in a wiring level on, for example, an upper surface of a dielectric layer. The thin-film resistor includes end portions tapered at an angle less than 90 degrees with respect to the upper surface. The tapered end portions provide increased surface area for making contact to the thin-film resistor without adversely affecting the resistance value of the thin-film resistor.

摘要翻译： 本发明涉及薄膜电阻器在布线层中的集成，例如铝后端（BEOL）技术。 薄膜电阻器形成在例如电介质层的上表面上的布线层中。 薄膜电阻器包括相对于上表面以小于90度的角度渐缩的端部。 锥形端部提供增加的表面积，用于与薄膜电阻器接触，而不会不利地影响薄膜电阻器的电阻值。

公开(公告)号：US06940117B2

公开(公告)日：2005-09-06

申请号：US10249550

申请日：2003-04-17

申请人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Joseph F. Shepard, Jr. ,  Kenneth J. Stein ,  Kunal Vaed

发明人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Joseph F. Shepard, Jr. ,  Kenneth J. Stein ,  Kunal Vaed

IPC分类号： H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/40 ,  H01L21/31604 ,  H01L28/55

摘要： The present invention provides a high-performance metal-insulator-metal (MIM) capacitor which contains a high-k dielectric, yet no substantial shorting of the MIM capacitor is observed. Specifically, shorting of the MIM capacitor is substantially prevented in the present invention by forming a passivation layer between the high-k dielectric layer and each of the capacitor's electrodes. The inventive MIM capacitor includes a first conductor; a first passivation layer located atop the first conductor; a high-k dielectric layer located atop the first passivation layer; a second passivation layer located atop the high k dielectric layer; and a second conductor located atop the second passivation layer.

摘要翻译： 本发明提供了一种高性能金属绝缘体金属（MIM）电容器，其包含高k电介质，但没有观察到MIM电容器的实质短路。 具体地说，在本发明中，通过在高k电介质层和电容器的电极之间形成钝化层，基本上防止了MIM电容器的短路。 本发明的MIM电容器包括第一导体; 位于第一导体顶部的第一钝化层; 位于第一钝化层顶部的高k电介质层; 位于高k电介质层顶部的第二钝化层; 以及位于第二钝化层顶部的第二导体。

公开(公告)号：US08609505B2

公开(公告)日：2013-12-17

申请号：US13359032

申请日：2012-01-26

申请人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Robert M. Rassel ,  Anthony K. Stamper

发明人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Robert M. Rassel ,  Anthony K. Stamper

IPC分类号： H01L27/06 ,  H01L27/07 ,  H01L21/20

CPC分类号： H01L27/0629 ,  H01L28/60

摘要： A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.

摘要翻译： 电容器结构包括半导体衬底; 位于所述半导体衬底上的第一电容器板，所述第一电容器板包括具有周围间隔物的多晶硅结构; 硅化物层，形成在所述第一电容器板的上表面的第一部分中; 电容器电介质层，形成在第一电容器板的上表面的第二部分上并且横向延伸超过间隔物以接触半导体衬底; 在层间电介质（ILD）中的接触，接触硅化物层的接触和ILD上的第一金属层; 以及在所述电容器电介质层上的第二电容器板，其中由所述第一电容器板，所述电容器介电层和所述第二电容器板以及金属 - 绝缘体 - 半导体（MIS）电容器形成金属 - 绝缘体 - 金属（MIM）电容器 由第二电容器板，电容器电介质层和半导体衬底形成。

公开(公告)号：US08569840B2

公开(公告)日：2013-10-29

申请号：US13370523

申请日：2012-02-10

申请人： Thomas A. Wallner ,  Ebenezer E. Eshun ,  Daniel J. Jaeger ,  Phung T. Nguyen

发明人： Thomas A. Wallner ,  Ebenezer E. Eshun ,  Daniel J. Jaeger ,  Phung T. Nguyen

IPC分类号： H01L29/70 ,  H01L29/73 ,  H01L29/78

CPC分类号： H01L21/8249 ,  H01L27/0623

摘要： A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.

摘要翻译： 形成高k栅极电介质层和金属栅极层，并图案化以暴露双极结型晶体管区域中的半导体表面，同时覆盖CMOS区域。 一次性材料部分形成在双极结型晶体管区域中暴露的半导体表面的一部分上。 沉积半导体层和电介质层，以形成包括CMOS区域中的半导体部分和介电栅极盖的栅极堆叠，以及在双极结型晶体管区域中的一次性材料部分上的包含台面的空腔。 选择性地去除一次性材料部分，并且包括外延部分和多晶部分的基层填充通过去除一次性材料部分而形成的空腔。 通过选择性外延形成的发射体填充台面中的空腔。